Artemis Milestone 2e: Address Device implemented, worked first try, 3-arch

Adds Slot/Endpoint/Input Control Context structs (32-byte layout only --
HCCPARAMS1.CSZ checked live and confirmed 0 against this driver's QEMU
target; 64-byte contexts refuse rather than silently mis-laying-out),
xhci_cmd_address_device(), and a new dev->connect_state
(idle/await-enable-slot/await-address-device) sequencing Enable Slot and
Address Device per connect. Input Context (what the command TRB's
parameter points at) and Device Context (what DCBAA[slot_id] points at)
are separate 64-byte-aligned allocations, lazily created once and reused
across every connect -- single-device driver scope, no free path needed.
A new EP0 Transfer Ring uses the same fixed-ring-plus-Link-TRB pattern as
the Command Ring.

Two facts checked live before writing any context code, not assumed:
HCCPARAMS1.CSZ (32-byte, confirmed) and PORTSC.PED at connect time
(already set -- PORTSC=0x00021203, SuperSpeed -- the test device
self-enables via USB3 link training, so no port-reset state machine was
needed this increment; USB2 would need one, untested). Both diagnostics
also added console_puts/println-based hex logging (xhci_log_hex32()) --
console_println() only takes string literals, no formatted print existed
on this driver's console path before now.

Verified live via QMP hotplug, all three architectures, succeeded on the
first attempt with no debugging needed: "enable slot succeeded" ->
"address device command submitted" -> "address device succeeded" on
every boot.

Also fixes a FABRIC-2.md dependency-direction error from the previous
commit (Address Device is 2f's prerequisite, not the reverse).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01HZ8kNoTuP63pbQtro4qvrm

include/starkernel/xhci_driver.h

@@ -57,6 +57,27 @@ typedef struct {
      * port_id whose Command Completion Event is still outstanding. */
     uint32_t            port_slot_id[XHCI_MAX_TRACKED_PORTS];
     uint32_t            pending_connect_port_id;
+    uint32_t            pending_connect_speed; /* PORTSC.Port Speed at connect time */
+
+    /* Milestone 2e: Address Device. This driver only ever addresses one
+     * device at a time (single-drive-at-a-time scope), so these are
+     * single, reused allocations rather than per-slot -- lazily allocated
+     * on the first connect that reaches xhci_cmd_address_device(), then
+     * reinitialised (not reallocated) on every subsequent connect. connect
+     * state tracks which command a still-outstanding completion event
+     * belongs to, since Enable Slot and Address Device are issued
+     * sequentially, not concurrently, for a given connect. */
+    enum {
+        XHCI_CONN_IDLE = 0,
+        XHCI_CONN_AWAIT_ENABLE_SLOT,
+        XHCI_CONN_AWAIT_ADDRESS_DEVICE
+    }                   connect_state;
+    uint32_t            pending_connect_slot_id;
+    void                *input_ctx;   /* Input Control Ctx + Slot Ctx + EP0 Ctx (96 bytes, 32-byte contexts) */
+    void                *device_ctx;  /* Slot Ctx + EP0 Ctx (64 bytes) -- DCBAA[slot_id] points here */
+    xhci_trb_t          *ep0_ring;    /* EP0 Transfer Ring, XHCI_RING_TRB_COUNT TRBs */
+    uint32_t            ep0_ring_cycle;
+    uint32_t            ep0_ring_enq;
 } xhci_dev_t;
 
 /*
@@ -137,4 +158,27 @@ void xhci_poll_events(void);
  */
 int xhci_cmd_enable_slot(xhci_dev_t *dev);
 
+/*
+ * xhci_cmd_address_device — build the Input Context (Slot + EP0, add-only),
+ *                            program DCBAA[slot_id] with the Device Context,
+ *                            allocate the EP0 Transfer Ring, and submit an
+ *                            Address Device command TRB.
+ *
+ * speed is the PORTSC.Port Speed value read live at the connect this call
+ * is servicing (xHCI 1.2 spec table 7-13 speed IDs) -- used to pick EP0's
+ * default Max Packet Size before any device descriptor has been read.
+ *
+ * Refuses (-2) if HCCPARAMS1.CSZ indicates 64-byte contexts -- only
+ * 32-byte contexts are implemented (see xhci.h's own doc comment on
+ * xhci_slot_ctx32_t).
+ *
+ * Called from xhci_poll_events()'s Command Completion handling once Enable
+ * Slot succeeds -- not called directly by other code.
+ *
+ * Returns 0 if the command was posted, -1 on allocation failure, -2 if
+ * 64-byte contexts are required.
+ */
+int xhci_cmd_address_device(xhci_dev_t *dev, uint32_t slot_id,
+                             uint32_t port_id, uint32_t speed);
+
 #endif /* STARKERNEL_XHCI_DRIVER_H */