starkernel: converge the tick path and wire the adaptive heartbeat (item 0.8)

Introduces src/starkernel/heartbeat.c as the shared top/bottom-half
implementation of heartbeat_init/tick/service/ticks/trust/state, replacing
the per-architecture duplicates in amd64/riscv64/aarch64 timer.c. Each
arch's timer.c now contributes only heartbeat_read_counter() (rdtsc /
rdtime / CNTPCT_EL0). Per the GAP-A1 ruling the top half stays counter+
latch only; heartbeat_service() (called every REPL idle iteration,
unconditionally per FABRIC.md's fidelity note) does the window/variance/
trust work outside interrupt context. vm_tick()'s call sites are
unchanged -- the engine still runs on the virtual tick.

Per FABRIC.md §26 (ruled 2026-08-03): wires Loop #7's execution-derived
stable/volatile signal into the physical re-arm period. vm_runtime.c's
existing Loop #7 site now calls heartbeat_set_adaptive_period_ns() with
tick_target_ns ratio-rescaled onto a 10ms kernel base (not the hosted
10us HEARTBEAT_TICK_NS -- see §26.3 for the scale mismatch). Each
architecture's re-arm function (apic_timer_rearm() on amd64/aarch64,
riscv64_timer_rearm()) now converts heartbeat_next_period_ns() to its
own raw counter units instead of a fixed constant; amd64 gained a
rearm function it didn't previously need, since periodic-mode auto-reload
never required one before this item.

Verified: all three architectures build with no new warnings and boot
cleanly to ok> with dict_hash=0x3d4e1daf289da94f, unchanged from the
pre-change baseline -- no regression. Verified NOT achieved: live re-arm
period variation under load. A temporary diagnostic (added and reverted)
confirmed Loop #7 never actually fired during a live QEMU session -- a
synthetic word-execution loop drove ~6,500 executions, past the 1000-tick
inference frequency, without tripping vm_tick_inference_engine()'s
pre-existing !vm->rolling_window.is_warm gate. That gate predates this
item and was not investigated -- out of scope. FABRIC.md's Done-when is
amended to record this honestly rather than claim it.

Punch list §25 item 0.8 complete (per amended, weaker acceptance -- see
the item's own annotation).

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>

src/starkernel/arch/riscv64/apic.c

@@ -17,6 +17,7 @@
 #include <stdint.h>
 
 static uint64_t s_timer_period_tsc = 0;
+static uint64_t s_time_hz = 0;   /* `time` CSR frequency (item 0.8/§26) */
 
 /* ---------------------------------------------------------------------------
  * SBI (Supervisor Binary Interface)
@@ -110,16 +111,30 @@ static int sbi_set_timer(uint64_t deadline)
  * no error anywhere — the single most likely silent failure of this driver.
  * Every path out of a timer interrupt must reach this function.
  *
+ * The step is @c heartbeat_next_period_ns() (item 0.8, §26) converted to
+ * `time`-counter ticks via @c s_time_hz, not the fixed @c s_timer_period_tsc
+ * used to seed the very first deadline in @c apic_timer_start() -- the
+ * latter remains @c apic_timer_period_tsc()'s return value for
+ * @c heartbeat_init()'s initial @c expected_delta, unchanged.
+ *
  * Called from @c riscv64_interrupt_handler() in @c interrupts.c on
  * @c scause cause 5.
  */
 void riscv64_timer_rearm(void)
 {
     uint64_t now;
+    uint64_t step;
 
     if (!s_sbi_time_ok) return;
 
-    s_next_deadline += s_timer_period_tsc;
+    step = (s_time_hz > 0)
+        ? (heartbeat_next_period_ns() * s_time_hz) / 1000000000ULL
+        : s_timer_period_tsc;
+    if (step == 0) {
+        step = 1;
+    }
+
+    s_next_deadline += step;
 
     /* If servicing ran long enough that the next deadline is already behind
      * us, resynchronise rather than burn through a backlog of instant
@@ -127,7 +142,7 @@ void riscv64_timer_rearm(void)
     now = rdtime();
     if (s_next_deadline <= now)
     {
-        s_next_deadline = now + s_timer_period_tsc;
+        s_next_deadline = now + step;
     }
 
     sbi_set_timer(s_next_deadline);
@@ -183,6 +198,7 @@ int apic_timer_init(uint64_t tsc_hz, uint32_t tick_hz)
         s_timer_period_tsc = tsc_hz / tick_hz;
     else
         s_timer_period_tsc = 10000000;
+    s_time_hz = tsc_hz;
     return 0;
 }