starkernel: item 4.3.5 -- amd64 I/O APIC + i8042 keyboard, interrupt-driven
Punch list §25 item 4.3.5 complete. New ioapic.c/i8042.c drivers (MADT-derived I/O APIC base, no hardcoded constants) plus a KBD-SCAN/KBD-DEBUG diagnostic word pair. Three real bugs found and fixed en route, all blocking this item's own acceptance: a fatal LAPIC spurious-vector crash (nothing had driven a real external interrupt through the I/O APIC before), OVMF leaving the keyboard device itself scanning-disabled (0xF4 fix), and isr.S's stub table only having individually-numbered stubs through vector 32 -- everything above that, including our IRQ1 vector 33, silently reported as vector 255 regardless of which IDT slot actually fired. Verified live via QEMU sendkey against KBD-SCAN: correct XT Set-1 make/break codes for two different keys. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
This commit is contained in:
Robert Allan James
co-authored by
Claude Sonnet 5
Claude Sonnet 5
parent
78ff335b97
commit
88eb73cfe8
@@ -273,14 +273,46 @@ int apic_init(BootInfo *boot_info) {
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lapic_write(APIC_REG_TPR, 0);
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/*
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* Issue a spurious EOI to clear any stale in-service interrupt left by
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* UEFI firmware. UEFI's last APIC timer tick may have fired just before
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* ExitBootServices with no subsequent EOI; the APIC's ISR then shows
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* vector 0x20 still "in service", which suppresses all future 0x20
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* delivery until an EOI is written. Issuing EOI here is always safe —
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* it is a no-op if the ISR is already clear.
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* Drain ALL stale in-service bits left by UEFI firmware, not just one.
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* UEFI's own interrupt handling commonly uses the same 0x20-based
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* legacy-IRQ vector remap convention this kernel does, and can leave
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* MORE THAN ONE vector "in service" when ExitBootServices() cuts it
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* off mid-handling (its own timer tick AND, per item 4.3.5's finding,
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* its own keyboard IRQ1 handling -- both land in the same 0x20-0x2F
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* range). A single EOI clears only the highest-priority stale bit;
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* firmware's other stale bit then sits permanently in-service and
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* silently demotes every future same-or-lower-class interrupt to the
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* spurious vector instead of its real one. EOI always clears whichever
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* ISR bit is currently highest-priority, so looping while any of the
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* 8 ISR registers (0x100-0x170, vectors 0-255) is nonzero drains all
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* of them. Bounded to 8 iterations -- one firmware is not expected to
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* leave more stale bits than that; if it does, stop rather than spin
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* forever on real hardware.
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*/
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lapic_write(APIC_REG_EOI, 0);
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{
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#define APIC_REG_ISR_BASE 0x100
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int drained;
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for (drained = 0; drained < 8; drained++) {
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int any_set = 0;
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for (int r = 0; r < 8; r++) {
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if (lapic_read(APIC_REG_ISR_BASE + (uint32_t)r * 0x10) != 0) {
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any_set = 1;
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break;
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}
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}
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if (!any_set) break;
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lapic_write(APIC_REG_EOI, 0);
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}
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console_puts("APIC: stale-ISR drain: ");
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{
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char buf[8]; int i = 0; uint32_t v = (uint32_t)drained;
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if (v == 0) buf[i++] = '0';
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else { char tmp[8]; int j = 0; while (v > 0) { tmp[j++] = (char)('0' + (v % 10)); v /= 10; } while (j > 0) buf[i++] = tmp[--j]; }
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buf[i] = '\0';
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console_puts(buf);
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}
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console_puts(" EOI(s) issued\n");
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}
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console_puts("APIC: initialized (xAPIC MMIO, TPR=0, SIVR=0x1FF, EOI-clear)\n");
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return 0;
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@@ -302,6 +334,20 @@ void apic_eoi(void) {
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lapic_write(APIC_REG_EOI, 0);
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}
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/**
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* @brief Return this CPU's xAPIC ID.
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*
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* Reads @c APIC_REG_ID and extracts bits 31:24, the xAPIC ID field. Used by
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* the I/O APIC driver (item 4.3.5) as the destination field when programming
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* a redirection entry — interrupts routed to this ID are delivered to the
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* current CPU's Local APIC.
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*
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* @return This CPU's 8-bit xAPIC ID.
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*/
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uint8_t apic_id(void) {
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return (uint8_t)(lapic_read(APIC_REG_ID) >> 24);
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}
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/* ============================================================================
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* APIC Timer
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* ============================================================================ */
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@@ -0,0 +1,150 @@
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/*
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StarForth — Steady-State Virtual Machine Runtime
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Copyright (c) 2023–2025 Robert A. James
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All rights reserved.
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This file is part of the StarForth project.
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Licensed under the StarForth License, Version 1.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at:
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https://github.com/star.4th@proton.me/StarForth/LICENSE.txt
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This software is provided "AS IS", WITHOUT WARRANTY OF ANY KIND,
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express or implied, including but not limited to the warranties of
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merchantability, fitness for a particular purpose, and noninfringement.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* i8042.c - PS/2 keyboard controller driver (amd64)
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*
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* Item 4.3.5 (FABRIC.md §27.5).
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*/
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#ifndef __STARKERNEL__
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#error "i8042.c is kernel-only"
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#endif
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#include <stdint.h>
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#include "starkernel/i8042.h"
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#include "console.h"
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#define I8042_DATA_PORT 0x60
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#define I8042_STATUS_PORT 0x64
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#define I8042_CMD_PORT 0x64
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#define I8042_STATUS_OUTPUT_FULL (1u << 0)
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#define I8042_STATUS_INPUT_FULL (1u << 1)
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#define I8042_CMD_READ_CONFIG 0x20
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#define I8042_CMD_WRITE_CONFIG 0x60
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#define I8042_CONFIG_IRQ1_ENABLE (1u << 0)
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#define I8042_DEV_CMD_ENABLE_SCANNING 0xF4
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#define I8042_DEV_ACK 0xFA
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/* Bounded wait -- command handshakes during one-time init only, never in
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* the interrupt path or a per-keystroke loop. */
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#define I8042_INIT_WAIT_ITERS 100000
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static inline void outb(uint16_t port, uint8_t val) {
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__asm__ volatile ("outb %0, %1" : : "a"(val), "Nd"(port));
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}
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static inline uint8_t inb(uint16_t port) {
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uint8_t val;
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__asm__ volatile ("inb %1, %0" : "=a"(val) : "Nd"(port));
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return val;
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}
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void i8042_init(void) {
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/* Drain any stale output byte left by firmware before enabling IRQ1 —
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* otherwise the first "interrupt" would really be this leftover byte
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* read via polling, not a real IRQ1 delivery. */
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while (inb(I8042_STATUS_PORT) & I8042_STATUS_OUTPUT_FULL) {
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(void)inb(I8042_DATA_PORT);
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}
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outb(I8042_CMD_PORT, I8042_CMD_READ_CONFIG);
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uint8_t config = inb(I8042_DATA_PORT);
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config |= I8042_CONFIG_IRQ1_ENABLE;
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outb(I8042_CMD_PORT, I8042_CMD_WRITE_CONFIG);
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outb(I8042_DATA_PORT, config);
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/* Tell the keyboard device itself to (re)enable scanning. OVMF's own
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* PS/2 driver commonly sends 0xF5 (disable scanning) to the device as
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* part of its own teardown before handoff, the same way it stops
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* driving the PIT/PIC -- the controller's IRQ1-enable bit above only
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* governs the controller, not whether the device generates scancodes
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* at all. Bounded waits: one-time init handshake, not steady-state
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* polling. */
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{
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int i;
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for (i = 0; i < I8042_INIT_WAIT_ITERS; i++) {
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if (!(inb(I8042_STATUS_PORT) & I8042_STATUS_INPUT_FULL)) break;
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}
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outb(I8042_DATA_PORT, I8042_DEV_CMD_ENABLE_SCANNING);
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for (i = 0; i < I8042_INIT_WAIT_ITERS; i++) {
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if (inb(I8042_STATUS_PORT) & I8042_STATUS_OUTPUT_FULL) {
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uint8_t resp = inb(I8042_DATA_PORT);
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if (resp == I8042_DEV_ACK) {
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console_println("i8042: keyboard ACKed enable-scanning");
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} else {
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console_println("i8042: keyboard responded (not ACK) to enable-scanning");
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}
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break;
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}
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}
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}
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console_println("i8042: IRQ1 enabled in controller config byte");
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}
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void i8042_drain_stale(void) {
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/* Edge-triggered IRQ1 + OBF already set at unmask time == no rising
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* edge ever again (the textbook "fires once, then never" pattern).
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* i8042_init()'s drain happens at M4; VM bootstrap runs for real wall
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* time between then and unmask, so re-drain immediately before. */
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while (inb(I8042_STATUS_PORT) & I8042_STATUS_OUTPUT_FULL) {
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(void)inb(I8042_DATA_PORT);
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}
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}
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/* Ring buffer: single producer (the ISR), single reader (i8042_pop_scancode(),
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* called from ordinary non-interrupt context, e.g. a diagnostic FORTH word).
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* 32 entries is far more than one QEMU test keypress burst can fill. */
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#define RING_SIZE 32
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static volatile uint8_t ring[RING_SIZE];
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static volatile uint8_t ring_head = 0; /* next slot the ISR writes */
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static volatile uint8_t ring_tail = 0; /* next slot the reader takes */
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/* Count of real keyboard IRQs serviced since boot -- a plain counter, no
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* I/O, is cheap enough to keep in the ISR itself and doubles as the
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* quickest way to confirm the interrupt path is alive without touching
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* the ring buffer at all. */
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volatile uint32_t g_i8042_isr_count = 0;
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void i8042_handle_irq(void) {
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/* Must always read 0x60, even to discard — otherwise OBF never clears
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* and the controller stops delivering further interrupts. */
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uint8_t scancode = inb(I8042_DATA_PORT);
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g_i8042_isr_count++;
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uint8_t next_head = (uint8_t)((ring_head + 1) % RING_SIZE);
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if (next_head != ring_tail) { /* drop the byte if the ring is full */
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ring[ring_head] = scancode;
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ring_head = next_head;
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}
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}
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int i8042_pop_scancode(uint8_t *out) {
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if (ring_tail == ring_head) return 0; /* empty */
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*out = ring[ring_tail];
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ring_tail = (uint8_t)((ring_tail + 1) % RING_SIZE);
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return 1;
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}
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@@ -49,11 +49,15 @@
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#include "console.h"
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#include "apic.h"
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#include "timer.h"
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#include "starkernel/i8042.h"
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/* Set by the FORTH dispatcher just before calling entry->func(vm).
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* Printed on fault to identify which word was executing. */
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volatile const char *g_sk_fault_word = (void *)0;
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/* Count of LAPIC spurious-vector interrupts since boot (item 4.3.5). */
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volatile uint32_t g_spurious_count = 0;
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#define IDT_ENTRIES 256
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#define INTERRUPT_GATE 0x8E
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@@ -342,6 +346,25 @@ void isr_common_handler(uint64_t vector,
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return;
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}
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/* Handle i8042 keyboard interrupt (item 4.3.5) */
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if (vector == I8042_KEYBOARD_VECTOR) {
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i8042_handle_irq();
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apic_eoi();
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return;
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}
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/* Spurious interrupt: normal occasional race per Intel SDM Vol.3 §10.9,
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* not a fault. No EOI -- the SDM is explicit that spurious-vector
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* interrupts must not be acknowledged. g_spurious_count is a cheap,
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* permanent diagnostic (item 4.3.5 found a real keyboard IRQ silently
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* misreported as spurious due to a missing dedicated ISR stub -- see
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* isr.S -- so a way to notice "spurious firing when it shouldn't be"
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* is worth keeping, not just scaffolding for that one investigation). */
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if (vector == APIC_SPURIOUS_VECTOR) {
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g_spurious_count++;
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return;
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}
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/* All other vectors are exceptions - print diagnostic and halt */
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console_println("\n=== INTERRUPT/EXCEPTION ===");
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@@ -0,0 +1,319 @@
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/*
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StarForth — Steady-State Virtual Machine Runtime
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Copyright (c) 2023–2025 Robert A. James
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All rights reserved.
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This file is part of the StarForth project.
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Licensed under the StarForth License, Version 1.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at:
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https://github.com/star.4th@proton.me/StarForth/LICENSE.txt
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This software is provided "AS IS", WITHOUT WARRANTY OF ANY KIND,
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express or implied, including but not limited to the warranties of
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merchantability, fitness for a particular purpose, and noninfringement.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* ioapic.c - I/O APIC driver (amd64)
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*
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* Item 4.3.5 (FABRIC.md §27.5). MADT parsing mirrors pci.c's RSDP -> XSDT ->
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* table-by-signature walk (the two files don't share a header for this —
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* same duplication pci.c already has relative to a hypothetical shared
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* acpi.c, not introduced fresh here).
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*/
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#ifndef __STARKERNEL__
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#error "ioapic.c is kernel-only"
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#endif
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#include <stddef.h>
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#include <stdint.h>
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#include "starkernel/ioapic.h"
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#include "console.h"
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#include "vmm.h"
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/* -------------------------------------------------------------------------
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* ACPI structures for MADT discovery
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* ------------------------------------------------------------------------- */
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typedef struct {
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uint8_t signature[8];
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uint8_t checksum;
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uint8_t oem_id[6];
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uint8_t revision;
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uint32_t rsdt_address;
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uint32_t length;
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uint64_t xsdt_address;
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uint8_t extended_checksum;
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uint8_t reserved[3];
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} __attribute__((packed)) Rsdp2;
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typedef struct {
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uint8_t signature[4];
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uint32_t length;
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uint8_t revision;
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uint8_t checksum;
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uint8_t oem_id[6];
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uint8_t oem_table_id[8];
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uint32_t oem_revision;
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uint32_t creator_id;
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uint32_t creator_revision;
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} __attribute__((packed)) AcpiHeader;
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typedef struct {
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AcpiHeader hdr;
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uint32_t local_apic_address;
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uint32_t flags;
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/* variable-length entries follow */
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} __attribute__((packed)) MadtHeader;
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typedef struct {
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uint8_t type; /* 1 = I/O APIC */
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uint8_t length; /* 12 */
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uint8_t io_apic_id;
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uint8_t reserved;
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uint32_t io_apic_address;
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uint32_t gsi_base;
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} __attribute__((packed)) MadtIoApic;
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typedef struct {
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uint8_t type; /* 2 = Interrupt Source Override */
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uint8_t length; /* 10 */
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uint8_t bus;
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uint8_t source; /* legacy ISA IRQ */
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uint32_t gsi;
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uint16_t flags; /* bits[1:0] polarity, bits[3:2] trigger mode */
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} __attribute__((packed)) MadtIntSrcOverride;
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#define MADT_TYPE_IOAPIC 1
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#define MADT_TYPE_INT_SRC 2
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#define ISO_POLARITY_MASK 0x3u
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#define ISO_POLARITY_HIGH 0x1u
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#define ISO_POLARITY_LOW 0x3u
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#define ISO_TRIGGER_MASK 0xCu
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#define ISO_TRIGGER_EDGE 0x4u
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#define ISO_TRIGGER_LEVEL 0xCu
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/* -------------------------------------------------------------------------
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* Module state
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* ------------------------------------------------------------------------- */
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#define MAX_OVERRIDES 16
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static uint64_t g_ioapic_base = 0;
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static uint32_t g_ioapic_gsi_base = 0;
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static int g_ioapic_ready = 0;
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static MadtIntSrcOverride g_overrides[MAX_OVERRIDES];
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static int g_override_count = 0;
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/* Cached low-dword redirection values, indexed by GSI - g_ioapic_gsi_base,
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* so ioapic_unmask_legacy_irq() can clear just the mask bit without having
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* to re-derive polarity/trigger from the override table again. */
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#define MAX_REDIR_ENTRIES 24
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static uint32_t g_redir_low[MAX_REDIR_ENTRIES];
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static int g_redir_valid[MAX_REDIR_ENTRIES];
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/* -------------------------------------------------------------------------
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* I/O APIC MMIO access (IOREGSEL @ +0x00, IOWIN @ +0x10)
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* ------------------------------------------------------------------------- */
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static void ioapic_write(uint8_t reg, uint32_t val) {
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volatile uint32_t *regsel = (volatile uint32_t *)(uintptr_t)(g_ioapic_base + 0x00);
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volatile uint32_t *iowin = (volatile uint32_t *)(uintptr_t)(g_ioapic_base + 0x10);
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*regsel = reg;
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*iowin = val;
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}
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/* -------------------------------------------------------------------------
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* ACPI MADT parsing
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* ------------------------------------------------------------------------- */
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static int sig4_eq(const uint8_t *p, const char *s) {
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return p[0] == (uint8_t)s[0] && p[1] == (uint8_t)s[1] &&
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p[2] == (uint8_t)s[2] && p[3] == (uint8_t)s[3];
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}
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static int sig8_eq(const uint8_t *p, const char *s) {
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int i;
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for (i = 0; i < 8; i++)
|
||||
if (p[i] != (uint8_t)s[i]) return 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int parse_madt(void *rsdp) {
|
||||
if (!rsdp) return -1;
|
||||
|
||||
Rsdp2 *r = (Rsdp2 *)rsdp;
|
||||
if (!sig8_eq(r->signature, "RSD PTR ")) return -1;
|
||||
if (r->revision < 2 || r->xsdt_address == 0) return -1;
|
||||
|
||||
AcpiHeader *xsdt = (AcpiHeader *)(uintptr_t)r->xsdt_address;
|
||||
if (!sig4_eq(xsdt->signature, "XSDT")) return -1;
|
||||
|
||||
uint32_t hdr_len = xsdt->length;
|
||||
if (hdr_len <= 36u) return -1;
|
||||
uint32_t n_entries = (hdr_len - 36u) / 8u;
|
||||
uint64_t *entries = (uint64_t *)((uint8_t *)xsdt + 36u);
|
||||
|
||||
uint32_t i;
|
||||
for (i = 0; i < n_entries; i++) {
|
||||
AcpiHeader *sdt = (AcpiHeader *)(uintptr_t)entries[i];
|
||||
if (!sig4_eq(sdt->signature, "APIC")) continue;
|
||||
|
||||
MadtHeader *madt = (MadtHeader *)sdt;
|
||||
uint8_t *p = (uint8_t *)madt + sizeof(MadtHeader);
|
||||
uint8_t *end = (uint8_t *)madt + madt->hdr.length;
|
||||
int found_ioapic = 0;
|
||||
|
||||
while (p + 2 <= end) {
|
||||
uint8_t type = p[0];
|
||||
uint8_t len = p[1];
|
||||
if (len == 0 || p + len > end) break;
|
||||
|
||||
if (type == MADT_TYPE_IOAPIC && !found_ioapic) {
|
||||
MadtIoApic *io = (MadtIoApic *)p;
|
||||
g_ioapic_base = io->io_apic_address;
|
||||
g_ioapic_gsi_base = io->gsi_base;
|
||||
found_ioapic = 1;
|
||||
} else if (type == MADT_TYPE_INT_SRC && g_override_count < MAX_OVERRIDES) {
|
||||
MadtIntSrcOverride *iso = (MadtIntSrcOverride *)p;
|
||||
g_overrides[g_override_count++] = *iso;
|
||||
}
|
||||
|
||||
p += len;
|
||||
}
|
||||
|
||||
return found_ioapic ? 0 : -1;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* -------------------------------------------------------------------------
|
||||
* Public API
|
||||
* ------------------------------------------------------------------------- */
|
||||
|
||||
int ioapic_init(void *acpi_rsdp) {
|
||||
if (parse_madt(acpi_rsdp) != 0) {
|
||||
console_println("I/O APIC: no MADT I/O APIC entry found");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (vmm_map_range(g_ioapic_base, g_ioapic_base, 0x1000u,
|
||||
VMM_FLAG_WRITABLE | VMM_FLAG_CACHE_DISABLE) != 0) {
|
||||
console_println("I/O APIC: failed to map MMIO page");
|
||||
return -1;
|
||||
}
|
||||
|
||||
g_ioapic_ready = 1;
|
||||
|
||||
console_puts("I/O APIC: base=0x");
|
||||
for (int s = 28; s >= 0; s -= 4)
|
||||
console_putc("0123456789abcdef"[((uint32_t)g_ioapic_base >> s) & 0xF]);
|
||||
console_puts(", gsi_base=");
|
||||
{
|
||||
char buf[16]; int i = 0; uint32_t v = g_ioapic_gsi_base;
|
||||
if (v == 0) buf[i++] = '0';
|
||||
else { char tmp[16]; int j = 0; while (v > 0) { tmp[j++] = (char)('0' + (v % 10)); v /= 10; } while (j > 0) buf[i++] = tmp[--j]; }
|
||||
buf[i] = '\0';
|
||||
console_puts(buf);
|
||||
}
|
||||
console_puts(", overrides=");
|
||||
{
|
||||
char buf[8]; int i = 0; uint32_t v = (uint32_t)g_override_count;
|
||||
if (v == 0) buf[i++] = '0';
|
||||
else { char tmp[8]; int j = 0; while (v > 0) { tmp[j++] = (char)('0' + (v % 10)); v /= 10; } while (j > 0) buf[i++] = tmp[--j]; }
|
||||
buf[i] = '\0';
|
||||
console_puts(buf);
|
||||
}
|
||||
console_println("");
|
||||
|
||||
/* TEMP DEBUG (item 4.3.5 investigation) */
|
||||
for (int oi = 0; oi < g_override_count; oi++) {
|
||||
console_puts(" override: source=");
|
||||
console_putc("0123456789abcdef"[(g_overrides[oi].source >> 4) & 0xF]);
|
||||
console_putc("0123456789abcdef"[g_overrides[oi].source & 0xF]);
|
||||
console_puts(" gsi=");
|
||||
{
|
||||
char buf[16]; int i = 0; uint32_t v = g_overrides[oi].gsi;
|
||||
if (v == 0) buf[i++] = '0';
|
||||
else { char tmp[16]; int j = 0; while (v > 0) { tmp[j++] = (char)('0' + (v % 10)); v /= 10; } while (j > 0) buf[i++] = tmp[--j]; }
|
||||
buf[i] = '\0';
|
||||
console_puts(buf);
|
||||
}
|
||||
console_puts(" flags=0x");
|
||||
console_putc("0123456789abcdef"[(g_overrides[oi].flags >> 12) & 0xF]);
|
||||
console_putc("0123456789abcdef"[(g_overrides[oi].flags >> 8) & 0xF]);
|
||||
console_putc("0123456789abcdef"[(g_overrides[oi].flags >> 4) & 0xF]);
|
||||
console_putc("0123456789abcdef"[g_overrides[oi].flags & 0xF]);
|
||||
console_println("");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ioapic_route_legacy_irq(uint8_t isa_irq, uint8_t vector, uint8_t dest_apic_id) {
|
||||
if (!g_ioapic_ready) return -1;
|
||||
|
||||
uint32_t gsi = isa_irq;
|
||||
uint32_t polarity = 0; /* active-high (ISA default) */
|
||||
uint32_t trigger = 0; /* edge (ISA default) */
|
||||
|
||||
int i;
|
||||
for (i = 0; i < g_override_count; i++) {
|
||||
if (g_overrides[i].source == isa_irq) {
|
||||
gsi = g_overrides[i].gsi;
|
||||
uint16_t flags = g_overrides[i].flags;
|
||||
if ((flags & ISO_POLARITY_MASK) == ISO_POLARITY_LOW) polarity = 1;
|
||||
if ((flags & ISO_TRIGGER_MASK) == ISO_TRIGGER_LEVEL) trigger = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (gsi < g_ioapic_gsi_base) return -1;
|
||||
uint32_t redir_index = gsi - g_ioapic_gsi_base;
|
||||
if (redir_index >= MAX_REDIR_ENTRIES) return -1;
|
||||
|
||||
uint32_t low = (uint32_t)vector
|
||||
| (polarity << 13)
|
||||
| (trigger << 15)
|
||||
| (1u << 16); /* masked until ioapic_unmask_legacy_irq() */
|
||||
uint32_t high = (uint32_t)dest_apic_id << 24;
|
||||
|
||||
ioapic_write((uint8_t)(0x10 + 2 * redir_index + 1), high);
|
||||
ioapic_write((uint8_t)(0x10 + 2 * redir_index), low);
|
||||
|
||||
g_redir_low[redir_index] = low;
|
||||
g_redir_valid[redir_index] = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ioapic_unmask_legacy_irq(uint8_t isa_irq) {
|
||||
if (!g_ioapic_ready) return;
|
||||
|
||||
uint32_t gsi = isa_irq;
|
||||
int i;
|
||||
for (i = 0; i < g_override_count; i++) {
|
||||
if (g_overrides[i].source == isa_irq) {
|
||||
gsi = g_overrides[i].gsi;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (gsi < g_ioapic_gsi_base) return;
|
||||
uint32_t redir_index = gsi - g_ioapic_gsi_base;
|
||||
if (redir_index >= MAX_REDIR_ENTRIES || !g_redir_valid[redir_index]) return;
|
||||
|
||||
uint32_t low = g_redir_low[redir_index] & ~(1u << 16);
|
||||
ioapic_write((uint8_t)(0x10 + 2 * redir_index), low);
|
||||
g_redir_low[redir_index] = low;
|
||||
}
|
||||
@@ -24,6 +24,7 @@
|
||||
.hidden isr_stub_table
|
||||
.hidden isr_stub0
|
||||
.hidden isr_stub32
|
||||
.hidden isr_stub33
|
||||
.hidden isr_stub_default
|
||||
.hidden isr_common_entry
|
||||
|
||||
@@ -155,7 +156,20 @@ isr_stub32:
|
||||
push 0x20
|
||||
jmp isr_common_entry
|
||||
|
||||
/* Default stub for other vectors (33-255) */
|
||||
/* Stub for i8042 keyboard IRQ1, routed via I/O APIC to vector 0x21 = 33
|
||||
* (item 4.3.5, FABRIC.md §27.5). Before this stub existed, vector 33 fell
|
||||
* through to isr_stub_default below, which unconditionally reports "255"
|
||||
* regardless of which IDT slot actually fired -- the CPU legitimately took
|
||||
* IDT[33] (confirmed via the LAPIC's own ISR register), but isr_common_handler
|
||||
* only ever saw vector 255 and treated a real keyboard IRQ as spurious,
|
||||
* silently skipping EOI and leaving vector 33 permanently stuck in-service. */
|
||||
.global isr_stub33
|
||||
isr_stub33:
|
||||
push 0
|
||||
push 33
|
||||
jmp isr_common_entry
|
||||
|
||||
/* Default stub for other vectors (34-255) */
|
||||
.global isr_stub_default
|
||||
isr_stub_default:
|
||||
push 0 /* fake error */
|
||||
@@ -177,7 +191,9 @@ isr_stub_table:
|
||||
.quad isr_stub28, isr_stub29, isr_stub30, isr_stub31
|
||||
/* Vector 32 = APIC Timer */
|
||||
.quad isr_stub32
|
||||
/* Vectors 33-255 default to unknown stub */
|
||||
.rept 223
|
||||
/* Vector 33 = i8042 keyboard IRQ1 (item 4.3.5) */
|
||||
.quad isr_stub33
|
||||
/* Vectors 34-255 default to unknown stub */
|
||||
.rept 222
|
||||
.quad isr_stub_default
|
||||
.endr
|
||||
|
||||
Reference in New Issue
Block a user