From 8e94522d106874ed6d456f7f0b3c83d9389469e1 Mon Sep 17 00:00:00 2001 From: Robert Allan James Date: Sat, 29 Aug 2026 10:28:22 -0400 Subject: [PATCH] Record trajectory beyond v2.5.0: Zynq FPGA next, after a "coloring in" hardening phase MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The next big milestone after the three-board bare-metal cut (v2.5.0) is transferring the battle-tested amd64/aarch64/riscv64 story to a Zynq (AMD Xilinx) FPGA SoC — configurable silicon with soft/hard CPU cores, PL fabric, and a non-standard memory map, a genuinely larger step than any prior board (expected on a new even-major line). Between v2.5.0 and the Zynq sits a "coloring in" period: hardening that thickens the shape of what exists rather than adding silicon (USB BOT/xHCI + block robustness, live-entropy and Zuse-cert hardening on real ASICs, SMP/multi-core + IRQ routing from the HAL notes, driver breadth) so the FPGA carries a production-honest shape forward. Authoritative form in ROADMAP.md "Beyond v2.5.0"; FABRIC-3.md tracks the same horizon in the post-release section and re-points G.6's Next at the v2.2.0/v2.4.0/v2.5.0 cadence. --- FABRIC-3.md | 17 ++++++++++++++--- capsules/BLOCK_MAP.md | 2 +- disk/artemis.img | Bin 31457280 -> 31457280 bytes docs/lithosananke/ROADMAP.md | 21 +++++++++++++++++++++ 4 files changed, 36 insertions(+), 4 deletions(-) diff --git a/FABRIC-3.md b/FABRIC-3.md index 82f24de..0adfe1a 100644 --- a/FABRIC-3.md +++ b/FABRIC-3.md @@ -3470,9 +3470,10 @@ this is what makes the image "as generic as possible." (READ CAPACITY10 → MSC device ready → READ10 CSW PASS). This mirrors the real SER5 flow: firmware boots the thumbdrive's ESP, and the OS's own storage rides the same USB BOT/xHCI path. Works for all three arches via the arch-mapped EFI boot name. -- **Next (v2.0.1):** G.4 requires real entropy on the SER5 — amd64 **RDRAND** backend behind - `rng_get_bytes()` (QEMU-verifiable: `qemu64` exposes RDRAND), then flashing this image to - a physical stick and the G.5 real-board boot attempt. +- **Next (v2.0.1→v2.2.0):** G.5 real-board proof on the SER5 (in hand) — boot the thumbdrive + image, live RDRAND entropy, real Zuse mint on a second stick — then extend per arch to + v2.4.0 (RasPi 5) and v2.5.0 (Milk-V). Authoritative cadence in `ROADMAP.md` + "Board-by-board hardware rollout". --- @@ -3492,3 +3493,13 @@ the punch lists above explicitly delimit what is excluded from each milestone: - Dirty-event granularity (1.11, blocked on 4.3) and the §17.4 framebuffer heat/decay design. - Re-run the DoE on the new substrate (§A 5.1). - First-touch allocation first-call-free. + +**Beyond v2.5.0 — Zynq FPGA, then a coloring-in period, decided 2026-08-29.** The next big +milestone after the three-board bare-metal cut (v2.5.0) is transferring the story to a +**Zynq FPGA** (configurable silicon — soft/hard cores, PL fabric, non-standard memory map) — +a genuinely larger step than any prior board, expected on a new even-major line. Between +v2.5.0 and starting the Zynq sits a **"coloring in"** hardening phase: making v2.5.0's +real-hardware story production-honest (USB BOT/xHCI + block robustness; live-entropy and +Zuse-cert hardening on real ASICs; SMP/multi-core + IRQ routing from the HAL notes; driver +breadth) so the FPGA carries a thickened, not thin, shape forward. Full form in +`ROADMAP.md` "Beyond v2.5.0 — Zynq FPGA is the next big milestone". diff --git a/capsules/BLOCK_MAP.md b/capsules/BLOCK_MAP.md index e631868..897edf1 100644 --- a/capsules/BLOCK_MAP.md +++ b/capsules/BLOCK_MAP.md @@ -1,5 +1,5 @@ # Capsule Block Manifest — Auto-generated - + diff --git a/disk/artemis.img b/disk/artemis.img index 742e383a26818e42d1e2efecc317c2f23ea18a08..263040c3ae7e326e3503206ea6a5cc217a8d2ae7 100644 GIT binary patch delta 5199 zcmeH~3sV$V8ipBZHH0xCIxvHBR|HmB9D-m7%j&AAh#&}RbVe@G5O-k#0SN}(0XrJa zAYKAug@{^SfOr96hczNGYDlyMO-KMEs2j8tB9~Z!N`gc7J?Hdkx7>fQ1yx^Ff6sZJ zK414VJzy{xUN(>t72+t-QWV6|;uvwP_=0F9z9?FYN^zX{lK8S{BfcVz7bn!HG(m#4 zCTd}An%QHKLV2MzVXg&!$~$C~-m#9NpMC-QdRQGet|&~U5tiC6Uo8vB-!--RHFR3RPIAo~D6_&ZT^#`uMXHmDNY` zvzEa5=>b}tqG(jLz9&Xedv92+D8b>8QAI&28>P?qMru`A4yA0zESN_V_?qb*yGvsP zRiBVrt!)cbm<)CrrO-a-3~66e?2pN}(+C3#RcWlP*o8LVa%vjA7%$Vmh@7e|-oWIG zM7~@*KV6a=kq&4(CAAezXdBb(NsFCsl5lul0}pp#Rrs!(hwq@BXlq3_M))2Hd-xsV z;U27N=auttFWUU8O{7J*pM)1boRcAqVa95QU#-+u45MxDT|(MGMU5I+U;Rp+9jDd^ zgL7kf_9e7yzYwJ z^{dAC=a(j!M0K*2aQUqjK5X`iT{!2k?c1cqmF*_t#!nn(NLThTR^#tZm)eShXrmt( zNsI6y5}vWBJYX+WGDrsja9-s|{LCTAcVI z2@gK;;3sax>h1VCK5`QY-)xXZzDdG2{6n?!wT9#4Bv8MrgWt#=D7M3^Q`znny=bpx zhe%IVKM8w;JRvQ4B+Xd8ns$fZ^vsmNCM zZ~C84^T(p6Q#HcntmrW5wGw>3oBj&s9+i>(UwbJE{sM@-A(S2(!TguQTsn7akS2`D zGIDkk=8@M^%ZETra)30myN64Oxj8g(Mb*nuaF|F@)T=;DnhwdzdDaqXyv`+EG!Zyo zMuJ5TMO6tvObUYZds`lt?w8G*PiBczY~`r^(@=_foq?DX25H6jO+0ZV_y|qhu)M*M z>R35N#wkEd(m~QiObVCAi?_E7Av!vG;#dAjMk3X zN|D1YASUHNI^6wFE+tJfhmxJL6Lc%2&2MZOrpW355R;6Ma>thQM8n{+#YFOaRYs4# zTuD(=6cCe2Ae~(`z$NuZr)c8f4jI`PD=B(-6o^SDA!WGDTPe-r`*ds=*(obTM&s(0 z6tyM*F{utxW^@6UA~F+bq99vF)7G!2$f+2JN!KAQG_`Xn`Hf37;de_$o~Iiq+BX2i zq;?ODWzC14)vkCskgpo+Gi5GI$bjD0{tMR3ol0SI7l98gYwrcCqOFP^L*Cw*@l0M& zxS8fYwat76-ww~CaH21PviuZsq5oIUa>{?)rn#+Y5=`=V<;BRml>LxTnCvP&@n*HN zTP5ApgXWpxWM zt9YW=&_@%q3kmY}j8q7vRXAkfAcSXc7_(X$E3s%%1R3kx2^r0DiK58<3J{aRAQfgt zbLm>^8Jbw$AfwIa&QetRZy+Y=AmyYS!kLRi17n}_Wj z*U)g;UKvHtUq_LD6%dnhAjMt|&`H;_VADC8_+->9j+%B~ps2_lh)G6B9ftRK;_%K1 zkz_0%)i$7fGM4Ww9I|i;!ph!e9xiwxg@%XxzUAo8eYq5QuLfe$Nl4an-1O2|&1qw! z$PO!uWpuvv4-|cH4Two~kmCQ8!lkbJr8JRSK@k3K^F4v*Sup+VnQSkly)HyZClB8o zuz;LA^KU@xOb%WeA-yz`CzkrH(~(5f!t0rmw0rF(ijqs!8zpHvq}ZT0H%bX@tE-+! z32_8@d*QAGkJPMx#iJt%dtw1c5Zu*qM4U~m=p#n|Ks0y;?!urHDrf% zoie(!Cy=7s7DHUpL2~mC$&$t@uiQ@)!HERv$yk5S#Ua}v3E?b@Jv@9MPlzQuw0X)X zVTXpItNVbMlmls5Sv!{&Rj1R0SBs1e_heJ_U=WB&Mo21W&v&G;jzqN3#IbmS^2u0> zb8*PRB?#|pO6TG4V*}#ISO&9-ge9nn+Ag0$m_uRqntc8|ym4C)U5g!wbG%9&dr4;%{X%yH7{aN523u zsU6Z?1D={^{|9Wx{{i@4K=W&XDRmnDQi*GDNqBA<5e>>7H4!xl<$!WTIiZ|UE+|)& u8)`C6H^rq3M{3lFIdX?ao`jL#m63PC$XoOO>e~U|at`)0Pxs$d*!&04|4Ie` delta 5196 zcmeH~jZ;+D8HZU}Sc!`uU%P7%0YxEzghWLsB7+}%3K3mJT_P$D;$StkA!?BVxyqp6 zA{mxMR~w-kU;wGo1)|W@Dr$pPq7g|DF=1l13Q~)tG(h@0=iGCX@lWW$%sX@6=lq^~ z-h21%vYV5WW0ylpkO`9nOF=GJ3D$x_m@L=`uLx5FrC=*e73>6iVVd9|I5s$`L**n(mS?2ih zvl`*VeS#LJFig6T+^>~2_KvG$MjVz;GK4zWD+3&EQtMo$er`T402iSS2{!F@xoj=3 zyy%v8A@F{P%#`DzR?1uJ>q#3dE7KOasO3#}#>KY!DB8siitY3c_?ViAyuWEtI+H&m za^r&Qq$ToAq}O*(-@)4ITWGzu&LJ&!x=q5L_xp;g+6P!on;pT!J!mHxN5rvuNqGK= zX*}GI)zMQb9v(njQ4&a6oOzIh6E_s{@EBGVPkVWI9BteAV=UaDLiRti4LobBQp?x= z`Xip5ini1uaXUM)JqfqumXVfR-wdpFJYLAdZfM^-xR{;T#WheyyR#SR6A{~hF)JWRfatl$;zsas?=8DDXVE8EHf2DwF<8>^L6b>tamA2@V@#K z`oo^f?TC;3$0Tn~Ev7xrr>#|Kq*@6Nf%$&wqX5F`MtcaZbh#O z_&3jgM)IH3{)=y~y@_?-)Dyg~zJrlVd(xuRyE z+)y)7?kEqGCu$a+=-C10W3Rtr`rhlZwN+H<5BwSjy)g5>=n#AHCDD#~sjYr@d@=8< z$Gz0@q^J71^dV`OgBb^UJ2t-j+CDLi&QZ&&l-FX!w|>~gf6_N(@KOnBb_`H7ycLLj z$SCLHovoi7D@x5>!!&XAiiBo*%9oK3tK-jsnB)q{@jw)p(sHwCBI=ri!r}yq`o9BW zk{=|Ux`0dHt~Arc(J%?gE&3@M*Z{<&P)I(%y3VD(%4N&REPk6L)ct7;MHN{-QV9j-cu}EBToE}>~V^$-vDA#A*6HW zy*$x2ygHUh_73|v`uu zF{+3oJ7wROkZr4yq8BfKm~;t}!o3#9LthDb*R@f!BnpV_)D0=@Zyj7ZSLwczjJMk?p@yY%C~~p+f=f>!MO8Sg6~~J# zJwOw#S0%JPK93@sAt1KXD5T8)uHusN_g~XQtZO1gt7P&If^f*fN^iB?e%c2-d}?e# zJQ-{BO$lW`3!!LP0uYm2A!Ux< z>uDUauo2-Oi*ECB6H`!l2-H)DmG<;oY!_nbG2PsAVu7W;fY$S z`EQdQjtoku=U50uXPjfXq=WQrhMr4R^<^|Mev+VMGFCtn4%rSF2&qExtuo2<5^<_N#)ux~nGS;JP31zs4QMBtM5R+;keb{rKOZv)Eny?#{(2Hy% zMeVL#T)G6wO+7t8yq2@E!!%JFK~M`BYd9T;Y=?G)A1QP^9NDpUvjzV8d?ghAOh?hO zC?FmJV1poj5 diff --git a/docs/lithosananke/ROADMAP.md b/docs/lithosananke/ROADMAP.md index 525062c..fe9c6e6 100644 --- a/docs/lithosananke/ROADMAP.md +++ b/docs/lithosananke/ROADMAP.md @@ -47,6 +47,27 @@ not a separate dev line): - **v2.5.0 — all three bare metal.** Adds Milk-V (riscv64) to the above; the Zkr (RNDR) backend live. This is the full "same story on all three arches on real silicon" cut. +**Beyond v2.5.0 — Zynq FPGA is the next big milestone, after a hardening phase.** Once the +three general-purpose boards close, the next major transfer is to a **Zynq (AMD Xilinx) +FPGA** SoC — the step where the battle-tested amd64/aarch64/riscv64 story rides on +configurable silicon. That is a genuinely bigger milestone than any single prior board: an +FPGA demands its platform be carried forward rather than ported with trivial +architecture-delta work, and it reshapes the hardware story (soft/hard CPU cores, PL fabric, +non-standard memory map, custom peripherals). Expect a new even-major line for it once the +coloring-in period below lands. + +**Before the FPGA — "coloring in", decided 2026-08-29.** The period between the all-three +bare-metal cut (v2.5.0) and starting the Zynq is finishing/hardening work that thickens the +shape of what already exists rather than adding new silicon. This is not idle time; it is +the point where v2.5.0's real-hardware story is made production-honest before the FPGA asks +to carry it further. Concrete items to define during it (draft scope, to be firmed at v2.5.0 +close): Zynq-preflight robustness of the USB BOT/xHCI and block paths; live-entropy and +Zuse-cert hardening on the three real boards; SMP/multi-core bring-up and IRQ routing on real +ASICs (parked in the HAL notes); driver set expansion beyond the three boards before +committing an FPGA port; and whatever v2.5.0's real-board validation surfaces. As boards +land and the v2.5.0 gates close, this list is edited down to the concrete coloring-in punch +list, and the Zynq becomes the even-major target after it. + QEMU remains the zero-degradation reference on every line; each `X.Y.0` must reproduce the QEMU acceptance story (`POST 1012/0/0` + `ok>`, block-fence Zuse true, backend entropy non-deterministic) on its board before it closes.