riscv64: integrate minimal flattened devicetree reader and switch timer to time CSR
Punch list §25 item 0.3 NOT complete. - Added `starkernel/fdt.h` and `fdt.c` for minimal read-only devicetree parsing: sufficient for boot-time lookups such as `timebase-frequency`. - Bootloader now captures the devicetree blob (DTB) from `EFI_DTB_TABLE_GUID` into `BootInfo::dtb`. - RISC-V timer subsystem now uses the `time` CSR as the primary timestamp source, abandoning the hardcoded `cycle` frequency assumption. - Timer rate is read from `timebase-frequency` in the DTB when accessible; otherwise, a fallback value is used with a RELATIVE trust level. - Integrated the SBI TIME extension for one-shot timer deadlines, ensuring re-arming occurs after each tick to avoid missing heartbeats. Verified: riscv64 builds clean, boots to the ok> prompt with no regression; `riscv64/timer.c` reports accurate frequencies on QEMU's default firmware. Signed-off-by: Robert Allan James <robert.allan.james@gmail.com>
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Robert Allan James
@@ -5,45 +5,92 @@
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*/
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/**
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* timer.c (riscv64) - Timer using rdcycle counter.
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* timer.c (riscv64) - Timer using the `time` CSR.
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*
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* RISC-V provides rdcycle (CPU cycle counter) and rdtime (wall-clock timer).
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* We use rdcycle as the primary timestamp source; frequency is estimated
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* at 1 GHz (QEMU virt default) and updated if firmware provides a hint.
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* RISC-V provides `cycle` (per-hart clock cycles) and `time` (fixed-frequency
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* wall clock). The primary timestamp source is `time`, read via rdtime, and
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* its rate comes from the devicetree property timebase-frequency.
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*
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* This was `cycle` at an assumed 1 GHz until punch-list item 0.3. Two things
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* forced the change: the SBI TIME extension arms deadlines against `time`, so
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* mixing the two counters would compare unrelated clocks; and `cycle` has no
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* discoverable frequency, so every heartbeat variance and TIME-TRUST figure
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* riscv64 produced before this was measured against a wrong expected interval
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* (FABRIC.md §16.2). Figures from before and after are not comparable.
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*/
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#include "timer.h"
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#include "console.h"
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#include "q48_16.h"
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#include "uefi.h"
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#include "starkernel/fdt.h"
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#include <stdint.h>
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/**
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* @brief Read the RISC-V CPU cycle counter (@c rdcycle).
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* @brief Read the RISC-V wall-clock counter (@c rdtime, CSR @c time 0xC01).
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*
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* Issues the @c RDCYCLE pseudo-instruction (a @c CSRRS on @c cycle,
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* CSR 0xC00) to read the 64-bit hardware cycle counter. On RISC-V the
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* cycle counter is a per-hart monotonically incrementing register whose
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* frequency equals the hart's clock rate — the architectural equivalent
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* of the x86-64 TSC.
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* @c time is the memory-mapped real-time counter mandated by the privileged
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* spec: fixed frequency, common to all harts, and — unlike @c cycle — its
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* rate is discoverable, published by firmware as the devicetree property
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* @c timebase-frequency.
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*
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* Unlike @c CNTPCT_EL0 on AArch64, @c cycle is not architecturally
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* synchronised across harts; this is acceptable for the single-hart
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* LithosAnanke build. The frequency is not provided by hardware CSR
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* (unlike AArch64's @c CNTFRQ_EL0); @c timer_init() assumes 1 GHz
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* for QEMU @c virt-machine compatibility.
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* This replaces the earlier @c rdcycle() source. Two reasons, and the first
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* is not optional:
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*
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* @return Current 64-bit cycle count; wraps at UINT64_MAX (about 584 years
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* at 1 GHz — not a practical concern).
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* - **The SBI TIME extension is defined against @c time.** @c sbi_set_timer()
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* takes an absolute value on this counter, so arming a timer from a
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* @c cycle reading would compare two unrelated clocks.
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* - **@c cycle's frequency is not discoverable**, which is why the previous
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* implementation hardcoded an assumed 1 GHz. Every heartbeat variance and
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* TIME-TRUST figure riscv64 has produced was therefore computed against a
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* wrong expected interval.
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*
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* @return Current 64-bit @c time value.
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*/
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static inline uint64_t rdcycle(void)
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static inline uint64_t rdtime(void)
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{
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uint64_t val;
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__asm__ volatile ("rdcycle %0" : "=r"(val));
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__asm__ volatile (
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"rdtime %0" : "=r"(val));
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return val;
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}
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static uint64_t s_counter_hz = 1000000000ULL; /* assume 1 GHz */
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/* Fallback when firmware publishes no devicetree, or none carrying
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* timebase-frequency. 10 MHz is the QEMU virt machine's value. Named rather
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* than inlined so that a boot running on the fallback is greppable and
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* obviously distinct from a discovered rate. */
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#define RISCV_TIMEBASE_HZ_FALLBACK 10000000ULL
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/**
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* @brief Print @p val in decimal via @c console_putc().
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*
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* Same shape as the file-local helper in @c arch/amd64/timer.c — there is no
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* shared decimal printer in @c console.h, and the freestanding build has no
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* @c printf(). Prints "0" for zero.
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*
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* @param val Value to print.
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*/
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static void print_dec(uint64_t val)
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{
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char buf[32];
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int i = 0;
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if (val == 0)
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{
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console_putc('0');
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return;
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}
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while (val > 0 && i < (int)sizeof(buf))
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{
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buf[i++] = (char)('0' + (val % 10));
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val /= 10;
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}
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while (i-- > 0)
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{
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console_putc(buf[i]);
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}
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}
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static uint64_t s_counter_hz = RISCV_TIMEBASE_HZ_FALLBACK;
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static uint64_t s_ns_per_tick = 0;
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static uint64_t s_base_count = 0;
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static uint64_t s_base_ns = 0;
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@@ -54,31 +101,44 @@ static TimeTrustState g_heartbeat;
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/*
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* @brief Initialise the RISC-V timer subsystem (M5 milestone).
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*
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* On RISC-V there is no architectural CSR that directly reports the
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* @c rdcycle frequency (unlike AArch64's @c CNTFRQ_EL0). The timer
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* subsystem therefore assumes 1,000,000,000 Hz (1 GHz), which matches
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* QEMU's @c virt machine default clock. Real hardware board support would
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* need to read the frequency from a device tree or firmware table and
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* update @c s_counter_hz before computing @c s_ns_per_tick.
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* RISC-V has no CSR reporting the counter frequency (unlike AArch64's
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* @c CNTFRQ_EL0), so the rate is read from the devicetree property
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* @c timebase-frequency, located via the blob the firmware publishes under
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* @c EFI_DTB_TABLE_GUID and carried in @c BootInfo::dtb.
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*
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* Steps performed:
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* 1. Snapshots @c rdcycle() into @c s_base_count as the ns origin.
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* 2. Computes @c s_ns_per_tick as @c (1e9 << 16) / @c s_counter_hz in
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* 1. Reads @c timebase-frequency from @c boot_info->dtb when present;
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* otherwise keeps @c RISCV_TIMEBASE_HZ_FALLBACK and says so on the console.
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* 2. Snapshots @c rdtime() into @c s_base_count as the ns origin.
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* 3. Computes @c s_ns_per_tick as @c (1e9 << 16) / @c s_counter_hz in
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* Q16.16 fixed-point to avoid floating-point in the freestanding build.
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* 3. Fills @c s_cal with the assumed frequency and sets
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* @c TIMER_TRUST_ABSOLUTE (the @c rdcycle counter is invariant by
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* specification once enabled, though its frequency is merely assumed
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* rather than measured).
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* 4. Fills @c s_cal, setting @c TIMER_TRUST_ABSOLUTE only when the rate came
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* from firmware. On the fallback the counter is still invariant, but its
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* scaling to real time is a guess — which is @c TIMER_TRUST_RELATIVE.
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*
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* @param boot_info Kernel @c BootInfo (device-tree / ACPI pointer); unused
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* at this milestone — clock frequency is hard-coded.
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* @param boot_info Kernel @c BootInfo; @c ::dtb supplies the counter rate.
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* NULL, or a NULL/invalid blob, selects the fallback.
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* @return 0 always.
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*/
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int timer_init(BootInfo *boot_info)
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{
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(void)boot_info;
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uint32_t hz = 0;
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int discovered = 0;
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s_base_count = rdcycle();
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/* Discover the counter rate rather than assuming it. The devicetree is
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* the only source: RISC-V has no CNTFRQ_EL0 equivalent. boot_info->dtb is
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* NULL when firmware published no devicetree, in which case the named
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* fallback stands and the banner says so. */
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if (boot_info && fdt_valid(boot_info->dtb))
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{
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if (fdt_prop_u32(boot_info->dtb, "timebase-frequency", &hz) && hz != 0)
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{
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s_counter_hz = (uint64_t)hz;
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discovered = 1;
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}
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}
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s_base_count = rdtime();
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s_base_ns = 0;
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s_ns_per_tick = (1000000000ULL << 16) / s_counter_hz;
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@@ -87,14 +147,19 @@ int timer_init(BootInfo *boot_info)
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s_cal.pit_hz_mean = 0;
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s_cal.converged = 1;
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s_cal.vm_mode = 1;
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s_cal.trust = TIMER_TRUST_ABSOLUTE;
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/* ABSOLUTE only when the rate came from firmware. On the fallback the
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* counter is still monotonic and invariant, but its scaling to real time
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* is a guess, which is exactly the RELATIVE case. */
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s_cal.trust = discovered ? TIMER_TRUST_ABSOLUTE : TIMER_TRUST_RELATIVE;
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console_println("Timer: RISC-V rdcycle timer initialised.");
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console_puts("Timer: RISC-V time CSR @ ");
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print_dec(s_counter_hz);
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console_println(discovered ? " Hz (devicetree)" : " Hz (FALLBACK, no devicetree)");
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return 0;
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}
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/**
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* @brief Return the assumed cycle-counter frequency in Hz.
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* @brief Return the `time` counter frequency in Hz.
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*
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* Returns @c s_counter_hz (initialised to 1,000,000,000 by the module).
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* Used by @c apic_timer_init() to compute the expected inter-tick period
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@@ -128,7 +193,7 @@ uint64_t timer_tsc_hz(void)
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*/
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uint64_t timer_now_ns(void)
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{
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uint64_t delta = rdcycle() - s_base_count;
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uint64_t delta = rdtime() - s_base_count;
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return s_base_ns + ((delta * s_ns_per_tick) >> 16);
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}
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@@ -190,18 +255,24 @@ void heartbeat_init(uint64_t tsc_hz, uint64_t tick_hz)
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/**
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* @brief Record one heartbeat tick and update the inter-tick deviation window.
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*
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* Reads @c rdcycle() and, if @c last_tsc is non-zero, records the signed
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* Reads @c rdtime() and, if @c last_tsc is non-zero, records the signed
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* deviation @c ((now - last_tsc) - expected_delta) into the circular
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* @c window.deltas[] buffer. Increments @c ticks and @c total_samples.
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* Sets @c trust = @c Q48_ONE unconditionally — the RISC-V cycle counter
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* Sets @c trust = @c Q48_ONE unconditionally — the RISC-V @c time counter
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* is invariant and needs no statistical quality estimate.
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*
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* Called from the RISC-V timer ISR stub (or its no-op placeholder) at
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* each periodic heartbeat period.
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* Must read the same counter the deadline was programmed against.
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* @c expected_delta is derived from @c timebase-frequency and is therefore in
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* @c time units; measuring the interval with @c cycle instead would difference
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* two unrelated clocks and produce exactly the wrong-expected-interval defect
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* that switching off @c rdcycle was meant to remove.
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*
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* Called from @c riscv64_interrupt_handler() on @c scause cause 5, after the
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* timer has been re-armed.
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*/
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void heartbeat_tick(void)
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{
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uint64_t now = rdcycle();
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uint64_t now = rdtime();
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if (g_heartbeat.last_tsc != 0) {
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int64_t delta = (int64_t)(now - g_heartbeat.last_tsc)
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- (int64_t)g_heartbeat.expected_delta;
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