Robert Allan JamesandClaude Sonnet 5
15672ce17c
First stage of the preemptive context-switching plan (see ~/.claude/plans/logical-snuggling-bear.md). Pure foundation work -- every arch's ISR now saves the full register set on interrupt entry, so a trap frame is in principle sufficient to resume execution anywhere it was taken. No FORTH-visible behavior changes. amd64: added FXSAVE/FXRSTOR, closing a genuine pre-existing correctness gap (not just future-preemption prep) -- confirmed live double-precision FP code reachable from ordinary interpreter dispatch (vm_runtime.c Loop #5/#6), and the ISR previously saved zero FP/SSE state. rbp repurposed as a fixed anchor so the 16-byte-aligned FXSAVE area can be carved out of an unpredictably-aligned rsp without disturbing existing argument reads. aarch64: extended the trap frame 672->800 bytes, adding v8-v15 (AAPCS64 callee-saved, previously excluded on call-site-only reasoning that doesn't hold for an async trap). riscv64: extended the trap frame 320->512 bytes, adding s0-s11 and fs0-fs11 (the latter still correctly gated behind sstatus.FS != Off). All 3 architectures re-verified clean boot to ok> under the new frames -- amd64 through hundreds of timer ticks with FXSAVE/FXRSTOR live on every interrupt, aarch64 through 987 ticks, riscv64 clean on the now-larger FS-conditional block. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_016UNhH1mhi52i6Qihh7ZV5S
228 lines
6.5 KiB
ArmAsm
228 lines
6.5 KiB
ArmAsm
/*
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* isr.S - Interrupt/exception stubs for amd64
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*
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* Stack on entry to ISR stub (after CPU pushes):
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* [rsp+0] = error code (if any, or pushed 0)
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* [rsp+8] = vector (pushed by stub)
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* [rsp+16] = RIP
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* [rsp+24] = CS
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* [rsp+32] = RFLAGS
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* [rsp+40] = RSP (if privilege change)
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* [rsp+48] = SS (if privilege change)
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*
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* For IRQs (vector >= 32), we return via IRETQ.
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* For exceptions (vector < 32), we halt.
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*/
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.intel_syntax noprefix
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.section .text
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/* Mark symbols referenced from C as hidden so the C compiler uses direct
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* RIP-relative addressing (LEA) rather than GOT indirection. Without this,
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* -fPIC code collapses the GOT reference to a direct MOV that reads the
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* symbol's *bytes* instead of its *address*, corrupting the IDT setup. */
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.hidden isr_stub_table
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.hidden isr_stub0
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.hidden isr_stub32
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.hidden isr_stub33
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.hidden isr_stub_default
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.hidden isr_common_entry
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.macro ISR_NOERR num
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.global isr_stub\num
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isr_stub\num:
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push 0 /* fake error code */
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push \num /* vector number */
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jmp isr_common_entry
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.endm
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.macro ISR_ERR num
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.global isr_stub\num
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isr_stub\num:
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/* error code already on stack from CPU */
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push \num /* vector number */
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jmp isr_common_entry
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.endm
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.global isr_common_entry
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isr_common_entry:
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/* Save all general-purpose registers */
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push rax
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push rbx
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push rcx
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push rdx
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push rsi
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push rdi
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push rbp
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push r8
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push r9
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push r10
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push r11
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push r12
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push r13
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push r14
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push r15
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/* Stack layout now:
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* [rsp+0] = r15
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* [rsp+8] = r14
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* ...
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* [rsp+112] = rax
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* [rsp+120] = vector
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* [rsp+128] = error
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* [rsp+136] = rip
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* [rsp+144] = cs
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* [rsp+152] = rflags
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*/
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/* FABRIC-3.md SXXVIII (Stage 0, preemptive-context-switch trap-frame
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* parity, 2026-09-13): FXSAVE/FXRSTOR added here to close a real,
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* pre-existing gap, not just a future-preemption nicety -- confirmed
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* live double-precision FP code reachable from ordinary interpreter
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* dispatch (vm_runtime.c's Loop #5/#6 physics inference, called from
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* vm_tick() during word execution, not just at boot). The GPR pushes
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* above only cover integer state; on x86-64 SysV all XMM registers are
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* caller-saved, meaning the compiler is free to leave a live value in
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* one between any two instructions of straight-line code -- an
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* asynchronous interrupt is not a call site the interrupted code's own
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* instructions know about, so nothing here previously guaranteed FP
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* state actually survived a timer tick landing mid-computation.
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*
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* rbp is repurposed below as a fixed anchor pointing at "rsp right after
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* the 15 GPR pushes" (rbp's own true pushed value already lives safely
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* on the stack above and is restored by the ordinary `pop rbp` later) --
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* FXSAVE requires a 16-byte-aligned address and rsp's alignment here is
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* unpredictable (the interrupt could have landed anywhere), so the
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* FXSAVE area is carved out and aligned separately, with rbp used to
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* keep addressing everything else at its original, fixed offsets
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* regardless of that adjustment. */
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mov rbp, rsp
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sub rsp, 528 /* 512-byte FXSAVE area + 16 slack for alignment */
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and rsp, -16
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fxsave [rsp]
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/* Set up arguments for isr_common_handler(vector, error, rip, cs, rflags, cr2) */
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mov rdi, [rbp + 120] /* vector */
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mov rsi, [rbp + 128] /* error */
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mov rdx, [rbp + 136] /* rip */
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mov rcx, [rbp + 144] /* cs */
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mov r8, [rbp + 152] /* rflags */
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mov r9, cr2 /* cr2 */
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/* Pass stack frame pointer (after pushes) as 7th argument */
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push rbp
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call isr_common_handler
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add rsp, 8
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fxrstor [rsp]
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mov rsp, rbp /* collapse back to right after the GPR pushes */
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/* Restore general-purpose registers */
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pop r15
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pop r14
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pop r13
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pop r12
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pop r11
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pop r10
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pop r9
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pop r8
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pop rbp
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pop rdi
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pop rsi
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pop rdx
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pop rcx
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pop rbx
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pop rax
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/* Remove vector and error code from stack */
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add rsp, 16
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/* Return from interrupt */
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iretq
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/* Exception/interrupt stubs (0-31 explicit) */
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ISR_NOERR 0
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ISR_NOERR 1
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ISR_NOERR 2
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ISR_NOERR 3
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ISR_NOERR 4
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ISR_NOERR 5
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ISR_NOERR 6
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ISR_NOERR 7
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ISR_ERR 8
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ISR_NOERR 9
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ISR_ERR 10
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ISR_ERR 11
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ISR_ERR 12
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ISR_ERR 13
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ISR_ERR 14
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ISR_NOERR 15
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ISR_NOERR 16
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ISR_ERR 17
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ISR_NOERR 18
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ISR_NOERR 19
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ISR_NOERR 20
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ISR_ERR 21
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ISR_NOERR 22
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ISR_NOERR 23
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ISR_NOERR 24
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ISR_NOERR 25
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ISR_NOERR 26
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ISR_NOERR 27
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ISR_NOERR 28
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ISR_NOERR 29
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ISR_ERR 30
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ISR_NOERR 31
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/* Stub for APIC Timer (vector 0x20 = 32) */
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/* Diagnostic: write raw 'I' to COM1 (0x3F8) when stub is entered.
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* If 'I' never appears in the serial log, the stub is never reached
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* (bad IDT entry or fault during CPU interrupt delivery). */
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.global isr_stub32
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isr_stub32:
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push 0
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push 0x20
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jmp isr_common_entry
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/* Stub for i8042 keyboard IRQ1, routed via I/O APIC to vector 0x21 = 33
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* (item 4.3.5, FABRIC-0.md §27.5). Before this stub existed, vector 33 fell
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* through to isr_stub_default below, which unconditionally reports "255"
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* regardless of which IDT slot actually fired -- the CPU legitimately took
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* IDT[33] (confirmed via the LAPIC's own ISR register), but isr_common_handler
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* only ever saw vector 255 and treated a real keyboard IRQ as spurious,
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* silently skipping EOI and leaving vector 33 permanently stuck in-service. */
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.global isr_stub33
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isr_stub33:
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push 0
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push 33
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jmp isr_common_entry
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/* Default stub for other vectors (34-255) */
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.global isr_stub_default
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isr_stub_default:
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push 0 /* fake error */
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push 255 /* unknown vector, will be logged */
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jmp isr_common_entry
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/* Use .data instead of .rodata so UEFI applies relocations */
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.section .data
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.align 8
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.global isr_stub_table
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isr_stub_table:
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.quad isr_stub0, isr_stub1, isr_stub2, isr_stub3
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.quad isr_stub4, isr_stub5, isr_stub6, isr_stub7
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.quad isr_stub8, isr_stub9, isr_stub10, isr_stub11
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.quad isr_stub12, isr_stub13, isr_stub14, isr_stub15
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.quad isr_stub16, isr_stub17, isr_stub18, isr_stub19
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.quad isr_stub20, isr_stub21, isr_stub22, isr_stub23
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.quad isr_stub24, isr_stub25, isr_stub26, isr_stub27
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.quad isr_stub28, isr_stub29, isr_stub30, isr_stub31
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/* Vector 32 = APIC Timer */
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.quad isr_stub32
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/* Vector 33 = i8042 keyboard IRQ1 (item 4.3.5) */
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.quad isr_stub33
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/* Vectors 34-255 default to unknown stub */
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.rept 222
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.quad isr_stub_default
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.endr
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