Robert Allan James
8e94522d10
The next big milestone after the three-board bare-metal cut (v2.5.0) is transferring the battle-tested amd64/aarch64/riscv64 story to a Zynq (AMD Xilinx) FPGA SoC — configurable silicon with soft/hard CPU cores, PL fabric, and a non-standard memory map, a genuinely larger step than any prior board (expected on a new even-major line). Between v2.5.0 and the Zynq sits a "coloring in" period: hardening that thickens the shape of what exists rather than adding silicon (USB BOT/xHCI + block robustness, live-entropy and Zuse-cert hardening on real ASICs, SMP/multi-core + IRQ routing from the HAL notes, driver breadth) so the FPGA carries a production-honest shape forward. Authoritative form in ROADMAP.md "Beyond v2.5.0"; FABRIC-3.md tracks the same horizon in the post-release section and re-points G.6's Next at the v2.2.0/v2.4.0/v2.5.0 cadence.
StarForth / LithosAnanke Documentation
This is the lithosananke branch: the bare-metal StarKernel side of the project
(contrast master, which is the hosted-VM-only side). Documentation follows the
two-tier model described in docs/CLAUDE.md: formal/ is the polished,
citable LaTeX tier; working/ is living design notes and drafts that feed it.
Everything else in this directory is branch- or subsystem-specific material that
doesn't fit either tier.
Layout
- formal/ — Three-volume LaTeX documentation set (research volumes,
practitioner books, standalone reports) plus the
scraps/fragment library it's assembled from. Audience: patent counsel, SSRN reviewers, licensees, hobbyists with hardware in hand. Seeformal/CLAUDE.mdfor authoring conventions. - working/ — Living documents: architecture design notes, DoE
experiment logs, hardware/platform notes, draft specs, academic-paper source
material, and an archive of superseded docs. Source material for
formal/. - 03-architecture/ — Tripod VM architecture constraints (Hera/Hermes/Artemis) and the word-level ACL system design.
- lithosananke/ — LithosAnanke kernel branch documentation: milestone roadmap, system architecture, HAL reference, kernel command-line argument design, and the amd64 APIC-timer ISR postmortem.
- birthing/ — VM birthing plan and status for the Hera-spawns- Hermes/Artemis constellation, plus three-architecture QEMU acceptance logs.
- patent/ — Provisional patent application source. Legal hold — ask Bob before touching anything in this directory.
- api/ — Generated Doxygen tag file and warnings log (gitignored; not part of the tracked doc tree).
- pptx/ — Elevator-pitch and deep-dive slide decks for different audiences (technical, non-technical, academic, PhD-level).
Current Active Work
- LithosAnanke M7/M7.1 — VM parity validation and init capsule architecture.
See
lithosananke/README.mdandlithosananke/M7.1.md. - Word-level ACL system — Phase 6 complete on
master; Phase 7 (LithosAnanke parity) is the next step. See03-architecture/word-acl/README.md. - Tripod VMs — Hera (governor), Hermes (messenger), Artemis (memory/block
storage). See
03-architecture/tripod/README.mdandbirthing/.
Contributing
- Place new material in
working/first; promote toformal/only when it's ready to be cited (seeformal/CLAUDE.mdfor promotion criteria). - Never touch
patent/,formal/patent/,formal/scraps/legal/, orworking/legal/without Bob's explicit instruction. - Add a
README.mdto any new category-level subdirectory, following the format used throughout this tree: orientation paragraph + bullet list of real files with one-line descriptions.