Robert Allan JamesandClaude Sonnet 5
9c8ad8f6ff
Enable Slot command TRB submitted via a new xhci_submit_command()/ xhci_cmd_enable_slot(), ring doorbell 0, confirmed by a real Command Completion Event on all three architectures -- the first time this driver has written a TRB rather than only reading the Event Ring (2d). Added the Command Ring's previously-missing Link TRB (xHCI 1.2 spec sec 4.9.2) for wraparound correctness. Port Register connect/disconnect handling, slot-ID/context bookkeeping, Address Device, and the callback surface into Section U's code are still open -- this is the discriminating first step, not full 2e. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01HZ8kNoTuP63pbQtro4qvrm
221 lines
11 KiB
C
221 lines
11 KiB
C
/*
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* xhci.h — xHCI (Extensible Host Controller Interface, USB 3.x) register
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* layout and shared constants for StarKernel's USB host controller driver.
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*
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* Register layout from the xHCI 1.2 specification. Four MMIO regions, each
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* reached via an offset from PCI BAR0:
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* Capability Registers — at BAR0 + 0, fixed layout, CAPLENGTH gives the
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* offset to Operational Registers
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* Operational Registers — at BAR0 + CAPLENGTH
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* Runtime Registers — at BAR0 + RTSOFF (read from Capability Registers)
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* Doorbell Array — at BAR0 + DBOFF (read from Capability Registers)
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*
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* Struct fields are `volatile`, naturally aligned, NOT __attribute__((packed))
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* — matching virtio_blk.c's precedent and its documented riscv64 lesson:
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* packed structs force byte-wise loads/stores on strict-alignment targets,
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* and QEMU's MMIO handlers for exact-width registers can misbehave under
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* byte-wise access. The xHCI spec's register layout is naturally aligned at
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* every offset, so this translates directly without padding tricks.
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*
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* QEMU's `qemu-xhci` device identifies as PCI vendor 0x1B36 (Red Hat, Inc.),
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* device 0x000D — confirmed live via QMP `query-pci` against a real running
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* instance (not assumed from memory), 2026-08-22.
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*/
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#ifndef STARKERNEL_XHCI_H
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#define STARKERNEL_XHCI_H
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#include <stdint.h>
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/* -------------------------------------------------------------------------
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* PCI identification
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* ------------------------------------------------------------------------- */
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#define XHCI_PCI_VENDOR_ID 0x1B36u /* Red Hat, Inc. (QEMU qemu-xhci) */
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#define XHCI_PCI_DEVICE_ID 0x000Du
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/* -------------------------------------------------------------------------
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* Capability Registers (BAR0 + 0)
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* ------------------------------------------------------------------------- */
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typedef struct {
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volatile uint8_t cap_length; /* offset to Operational Registers */
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volatile uint8_t reserved0;
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volatile uint16_t hci_version; /* BCD xHCI spec version */
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volatile uint32_t hcs_params1; /* MaxSlots[7:0], MaxIntrs[18:8], MaxPorts[31:24] */
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volatile uint32_t hcs_params2; /* IST, ERST Max, scratchpad buffer counts */
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volatile uint32_t hcs_params3; /* U1/U2 device exit latencies */
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volatile uint32_t hcc_params1; /* AC64, BNC, CSZ, xECP pointer[31:16], etc. */
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volatile uint32_t db_off; /* Doorbell Array offset (low 2 bits reserved) */
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volatile uint32_t rts_off; /* Runtime Register Space offset (low 5 bits reserved) */
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volatile uint32_t hcc_params2;
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} xhci_cap_regs_t;
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#define XHCI_HCSPARAMS1_MAX_SLOTS(v) ((uint32_t)(v) & 0xFFu)
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#define XHCI_HCSPARAMS1_MAX_INTRS(v) (((uint32_t)(v) >> 8) & 0x7FFu)
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#define XHCI_HCSPARAMS1_MAX_PORTS(v) (((uint32_t)(v) >> 24) & 0xFFu)
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/* HCSPARAMS2: Max Scratchpad Buffers is a 10-bit field split across two
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* non-adjacent locations (xHCI 1.2 spec table 5-13) — Hi bits[25:21],
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* Lo bits[31:27]. Zero means the controller needs no scratchpad buffers
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* (common for simple emulated controllers, but verify live, not assumed). */
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#define XHCI_HCSPARAMS2_MAX_SCRATCHPAD_BUFS(v) \
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((((uint32_t)(v) >> 21) & 0x1Fu) << 5 | (((uint32_t)(v) >> 27) & 0x1Fu))
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/* -------------------------------------------------------------------------
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* Operational Registers (BAR0 + cap_length)
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* ------------------------------------------------------------------------- */
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typedef struct {
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volatile uint32_t usb_cmd; /* Run/Stop, HC Reset, Interrupter Enable, ... */
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volatile uint32_t usb_sts; /* HCHalted, HSE, EINT, PCD, CNR, HCE */
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volatile uint32_t page_size; /* bit N set => 2^(N+12)-byte pages supported */
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volatile uint32_t reserved0[2];
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volatile uint32_t dn_ctrl; /* Device Notification Control */
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volatile uint64_t crcr; /* Command Ring Control Register */
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volatile uint32_t reserved1[4];
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volatile uint64_t dcbaap; /* Device Context Base Address Array Pointer */
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volatile uint32_t config; /* MaxSlotsEn[7:0] */
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/* Port Register Sets follow at a fixed offset (0x400 from Operational
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* base), not contiguous with the fields above — accessed via
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* xhci_port_regs() below, not as a struct member. */
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} xhci_op_regs_t;
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/* USBCMD bits */
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#define XHCI_USBCMD_RUN (1u << 0) /* Run/Stop: 1 = run */
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#define XHCI_USBCMD_HCRST (1u << 1) /* HC Reset */
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#define XHCI_USBCMD_INTE (1u << 2) /* Interrupter Enable */
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#define XHCI_USBCMD_HSEE (1u << 3) /* Host System Error Enable */
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/* USBSTS bits */
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#define XHCI_USBSTS_HCH (1u << 0) /* HC Halted */
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#define XHCI_USBSTS_HSE (1u << 2) /* Host System Error */
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#define XHCI_USBSTS_EINT (1u << 3) /* Event Interrupt */
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#define XHCI_USBSTS_PCD (1u << 4) /* Port Change Detect */
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#define XHCI_USBSTS_CNR (1u << 11) /* Controller Not Ready */
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#define XHCI_USBSTS_HCE (1u << 12) /* Host Controller Error */
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/* CRCR bits (low bits of the 64-bit register; pointer occupies bits[63:6]) */
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#define XHCI_CRCR_RCS (1ull << 0) /* Ring Cycle State */
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#define XHCI_CRCR_CS (1ull << 1) /* Command Stop */
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#define XHCI_CRCR_CA (1ull << 2) /* Command Abort */
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#define XHCI_CRCR_CRR (1ull << 3) /* Command Ring Running (read-only) */
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#define XHCI_CRCR_PTR_MASK (~0x3Full) /* pointer must be 64-byte aligned */
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/* CONFIG */
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#define XHCI_CONFIG_MAX_SLOTS_EN(n) ((uint32_t)(n) & 0xFFu)
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/* Port Register Set — array at Operational base + 0x400, 0x10 bytes each,
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* indexed 0..(MaxPorts-1) for ports numbered 1..MaxPorts. */
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typedef struct {
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volatile uint32_t portsc; /* Port Status and Control */
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volatile uint32_t portpmsc; /* Port Power Management Status and Control */
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volatile uint32_t portli; /* Port Link Info */
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volatile uint32_t porthlpmc; /* Port Hardware LPM Control */
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} xhci_port_regs_t;
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#define XHCI_PORT_REGS_OFFSET 0x400u
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/* PORTSC bits (subset needed for hotplug + reset) */
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#define XHCI_PORTSC_CCS (1u << 0) /* Current Connect Status */
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#define XHCI_PORTSC_PED (1u << 1) /* Port Enabled/Disabled */
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#define XHCI_PORTSC_PR (1u << 4) /* Port Reset */
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#define XHCI_PORTSC_PLS_MASK (0xFu << 5) /* Port Link State */
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#define XHCI_PORTSC_PP (1u << 9) /* Port Power */
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#define XHCI_PORTSC_SPEED_MASK (0xFu << 10)
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#define XHCI_PORTSC_CSC (1u << 17) /* Connect Status Change */
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#define XHCI_PORTSC_PEC (1u << 18) /* Port Enabled/Disabled Change */
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#define XHCI_PORTSC_PRC (1u << 21) /* Port Reset Change */
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/* Writing 1 to a _C (change) bit clears it (RW1CS) — writing 0 has no effect.
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* PORTSC also has RW1CS bits interleaved with RW bits; always read-modify-
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* write with the change bits masked to 0 unless intentionally clearing one,
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* to avoid accidentally acknowledging an event by a stray read-modify-write. */
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/* -------------------------------------------------------------------------
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* Runtime Registers (BAR0 + rts_off)
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* ------------------------------------------------------------------------- */
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typedef struct {
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volatile uint32_t iman; /* Interrupt Management: bit0=IP, bit1=IE */
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volatile uint32_t imod; /* Interrupt Moderation */
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volatile uint32_t erstsz; /* Event Ring Segment Table Size */
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volatile uint32_t reserved0;
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volatile uint64_t erstba; /* Event Ring Segment Table Base Address */
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volatile uint64_t erdp; /* Event Ring Dequeue Pointer; bit3=EHB */
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} xhci_intr_regs_t;
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typedef struct {
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volatile uint32_t mf_index; /* Microframe Index */
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volatile uint32_t reserved0[7];
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/* Interrupter Register Sets follow, one xhci_intr_regs_t per interrupter,
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* starting immediately after this 0x20-byte header. Interrupter 0 is
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* accessed via xhci_intr_regs_t at (runtime_base + 0x20). */
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} xhci_runtime_regs_t;
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#define XHCI_IMAN_IP (1u << 0) /* Interrupt Pending */
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#define XHCI_IMAN_IE (1u << 1) /* Interrupt Enable */
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#define XHCI_ERDP_EHB (1ull << 3) /* Event Handler Busy */
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#define XHCI_ERDP_PTR_MASK (~0xFull) /* pointer occupies bits[63:4] */
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/* -------------------------------------------------------------------------
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* Doorbell Array (BAR0 + db_off) — array of uint32_t, one per device slot
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* plus doorbell 0 for the Command Ring. Write-only.
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* ------------------------------------------------------------------------- */
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typedef volatile uint32_t xhci_doorbell_t;
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#define XHCI_DB_TARGET(ep) ((uint32_t)(ep) & 0xFFu) /* 0 = command ring */
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#define XHCI_DB_STREAM_ID(sid) (((uint32_t)(sid) & 0xFFFFu) << 16)
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/* -------------------------------------------------------------------------
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* TRB (Transfer Request Block) — 16 bytes, the unit of both Command Ring
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* and Event Ring entries (and Transfer Rings, used later for BOT I/O).
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* ------------------------------------------------------------------------- */
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typedef struct {
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volatile uint64_t parameter;
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volatile uint32_t status;
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volatile uint32_t control;
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} xhci_trb_t;
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#define XHCI_TRB_CONTROL_CYCLE (1u << 0) /* Cycle bit */
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#define XHCI_TRB_CONTROL_TYPE_SHIFT 10
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#define XHCI_TRB_CONTROL_TYPE_MASK (0x3Fu << XHCI_TRB_CONTROL_TYPE_SHIFT)
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#define XHCI_TRB_TYPE(ctrl) (((ctrl) & XHCI_TRB_CONTROL_TYPE_MASK) >> XHCI_TRB_CONTROL_TYPE_SHIFT)
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/* TRB types used by this driver (subset — xHCI defines many more) */
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#define XHCI_TRB_TYPE_LINK 6 /* ring-wraparound marker, Command/Transfer Rings only */
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#define XHCI_TRB_TYPE_ENABLE_SLOT_CMD 9
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#define XHCI_TRB_TYPE_ADDRESS_DEVICE_CMD 11
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#define XHCI_TRB_TYPE_TRANSFER_EVENT 32
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#define XHCI_TRB_TYPE_COMMAND_COMPLETION_EVT 33
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#define XHCI_TRB_TYPE_PORT_STATUS_CHANGE_EVT 34
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/* Control bits used only by Link TRBs */
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#define XHCI_TRB_CONTROL_TC (1u << 1) /* Toggle Cycle */
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/* Command Completion Event TRB layout (xHCI 1.2 spec table 6-32):
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* parameter[63:4] = Command TRB Pointer, status[31:24] = Completion Code,
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* status[23:0] = unused here, control[31:24] = Slot ID (Enable Slot's
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* result, also present on Address Device completions). */
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#define XHCI_EVT_COMPLETION_CODE(status) (((uint32_t)(status) >> 24) & 0xFFu)
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#define XHCI_EVT_SLOT_ID(control) (((uint32_t)(control) >> 24) & 0xFFu)
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#define XHCI_COMPLETION_CODE_SUCCESS 1u
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/* -------------------------------------------------------------------------
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* Ring sizing — decided up front per Milestone 2's punch list (2a).
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*
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* Fixed, single-page rings: 256 TRBs x 16 bytes = 4096 bytes = one page.
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* This project's usage (MSC hotplug detection + read/write to one drive at
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* a time) does not need a high-throughput, dynamically-growable ring —
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* matches this codebase's existing preference for fixed, page-sized
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* allocations over dynamic growth (e.g. KRD_MAX_BLOCKS's fixed 1024-block
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* RAMDRIVE). One Command Ring, one Event Ring (Interrupter 0 only — this
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* driver does not use multiple interrupters).
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* ------------------------------------------------------------------------- */
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#define XHCI_RING_TRB_COUNT 256u
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#define XHCI_RING_BYTES (XHCI_RING_TRB_COUNT * sizeof(xhci_trb_t))
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#endif /* STARKERNEL_XHCI_H */
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