512 lines
16 KiB
C
512 lines
16 KiB
C
/*
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StarForth — Steady-State Virtual Machine Runtime
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Copyright (c) 2023–2025 Robert A. James
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All rights reserved.
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This file is part of the StarForth project.
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Licensed under the StarForth License, Version 1.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at:
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https://github.com/star.4th@proton.me/StarForth/LICENSE.txt
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This software is provided "AS IS", WITHOUT WARRANTY OF ANY KIND,
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express or implied, including but not limited to the warranties of
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merchantability, fitness for a particular purpose, and noninfringement.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#ifndef VM_ASM_OPT_RISCV64_H
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#define VM_ASM_OPT_RISCV64_H
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#include "vm.h"
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#include <stdint.h>
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/*
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* Configuration: Define USE_ASM_OPT=1 to enable assembly optimizations
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*/
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#ifndef USE_ASM_OPT
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#define USE_ASM_OPT 0
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#endif
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/*
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* RISC-V 64 Architecture Notes:
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* ==============================
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*
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* Register ABI (RV64GC / rv64gc):
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* - x0 (zero): hardwired zero
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* - x1 (ra): return address
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* - x2 (sp): stack pointer
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* - x3 (gp): global pointer
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* - x4 (tp): thread pointer
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* - x5–x7 (t0–t2): temporaries (caller-saved)
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* - x8–x9 (s0–s1): callee-saved / frame pointer
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* - x10–x17 (a0–a7): argument/return (caller-saved)
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* - x18–x27 (s2–s11): callee-saved
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* - x28–x31 (t3–t6): temporaries (caller-saved)
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*
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* Key differences vs x86_64 / ARM64:
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* - Pure load/store architecture — all ops work on registers
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* - No flags register; overflow detection requires explicit instructions
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* - No conditional move in base ISA (Zicond ext adds czero.eqz/czero.nez)
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* - No string-comparison instructions; byte loops required
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* - M extension: mul, mulh, div, rem — all present in rv64gc
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* - B extension (Zba/Zbb/Zbc): clz, ctz, cpop, etc. — NOT guaranteed in rv64gc
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*
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* Branchless min/max without Zicond:
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* slt t0, a, b # t0 = (a < b) ? 1 : 0
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* neg t0, t0 # t0 = (a < b) ? -1 : 0 (all-ones mask or zero)
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* sub t1, a, b # t1 = a - b
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* and t1, t1, t0 # t1 = (a-b) if a<b, else 0
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* add res, b, t1 # res = b + (a-b if a<b) = min(a,b)
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*
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* Overflow detection (no flags):
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* add res, a, b
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* # signed overflow iff same-sign operands produce opposite-sign result
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* xor t0, a, b # t0[63]=0 means same sign
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* xor t1, a, res # t1[63]=1 means sign changed
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* srai t0, t0, 63 # 0 or -1
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* srai t1, t1, 63 # 0 or -1
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* xori t0, t0, -1 # invert: -1 -> 0, 0 -> -1
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* and ovf, t0, t1 # -1 iff overflow
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* snez ovf, ovf # 0 or 1
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*/
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#if USE_ASM_OPT
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/* ============================================================================
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* OPTIMIZATION 1: Stack Operations
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* ============================================================================
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*/
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static inline void vm_push_asm(VM *vm, cell_t value) {
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int error = 0;
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__asm__ __volatile__(
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"lw t0, %[dsp]\n\t" /* t0 = dsp */
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"li t1, 1022\n\t"
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"bge t0, t1, 1f\n\t" /* branch if dsp >= 1022 (overflow) */
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"addi t0, t0, 1\n\t" /* dsp++ */
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"sw t0, %[dsp]\n\t"
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"slli t1, t0, 3\n\t" /* t1 = dsp * 8 */
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"add t1, %[stack], t1\n\t" /* t1 = &data_stack[dsp] */
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"sd %[val], 0(t1)\n\t" /* store value */
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"sw zero, %[err]\n\t"
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"j 2f\n\t"
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"1:\n\t"
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"li t0, 1\n\t"
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"sw t0, %[err]\n\t"
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"2:\n\t"
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: [dsp]"+m"(vm->dsp),
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[err]"=m"(error)
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: [val]"r"(value),
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[stack]"r"(vm->data_stack)
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: "t0", "t1", "memory"
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);
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if (__builtin_expect(error, 0)) {
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vm->error = 1;
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}
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}
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static inline cell_t vm_pop_asm(VM *vm) {
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cell_t value = 0;
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int error = 0;
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__asm__ __volatile__(
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"lw t0, %[dsp]\n\t"
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"bltz t0, 1f\n\t" /* branch if dsp < 0 (underflow) */
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"slli t1, t0, 3\n\t"
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"add t1, %[stack], t1\n\t"
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"ld %[val], 0(t1)\n\t"
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"addi t0, t0, -1\n\t"
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"sw t0, %[dsp]\n\t"
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"sw zero, %[err]\n\t"
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"j 2f\n\t"
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"1:\n\t"
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"li t0, 1\n\t"
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"sw t0, %[err]\n\t"
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"mv %[val], zero\n\t"
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"2:\n\t"
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: [dsp]"+m"(vm->dsp),
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[val]"=r"(value),
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[err]"=m"(error)
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: [stack]"r"(vm->data_stack)
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: "t0", "t1", "memory"
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);
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if (__builtin_expect(error, 0)) {
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vm->error = 1;
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}
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return value;
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}
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static inline void vm_rpush_asm(VM *vm, cell_t value) {
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int error = 0;
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__asm__ __volatile__(
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"lw t0, %[rsp]\n\t"
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"li t1, 1022\n\t"
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"bge t0, t1, 1f\n\t"
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"addi t0, t0, 1\n\t"
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"sw t0, %[rsp]\n\t"
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"slli t1, t0, 3\n\t"
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"add t1, %[stack], t1\n\t"
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"sd %[val], 0(t1)\n\t"
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"sw zero, %[err]\n\t"
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"j 2f\n\t"
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"1:\n\t"
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"li t0, 1\n\t"
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"sw t0, %[err]\n\t"
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"2:\n\t"
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: [rsp]"+m"(vm->rsp),
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[err]"=m"(error)
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: [val]"r"(value),
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[stack]"r"(vm->return_stack)
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: "t0", "t1", "memory"
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);
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if (__builtin_expect(error, 0)) {
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vm->error = 1;
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}
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}
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static inline cell_t vm_rpop_asm(VM *vm) {
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cell_t value = 0;
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int error = 0;
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__asm__ __volatile__(
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"lw t0, %[rsp]\n\t"
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"bltz t0, 1f\n\t"
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"slli t1, t0, 3\n\t"
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"add t1, %[stack], t1\n\t"
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"ld %[val], 0(t1)\n\t"
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"addi t0, t0, -1\n\t"
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"sw t0, %[rsp]\n\t"
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"sw zero, %[err]\n\t"
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"j 2f\n\t"
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"1:\n\t"
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"li t0, 1\n\t"
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"sw t0, %[err]\n\t"
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"mv %[val], zero\n\t"
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"2:\n\t"
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: [rsp]"+m"(vm->rsp),
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[val]"=r"(value),
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[err]"=m"(error)
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: [stack]"r"(vm->return_stack)
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: "t0", "t1", "memory"
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);
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if (__builtin_expect(error, 0)) {
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vm->error = 1;
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}
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return value;
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}
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/* ============================================================================
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* OPTIMIZATION 2: Arithmetic with Overflow Detection
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* ============================================================================
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*
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* RISC-V has no flags register. Overflow is detected by inspecting operand
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* and result sign bits directly.
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*
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* Signed addition overflows iff operands have the same sign and the result
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* has the opposite sign:
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* ovf = ~(a XOR b)[63] AND (a XOR result)[63]
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* ============================================================================
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*/
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static inline int vm_add_check_overflow(cell_t a, cell_t b, cell_t *result) {
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cell_t res;
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cell_t ovf;
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__asm__(
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"add %[res], %[a], %[b]\n\t"
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"xor t0, %[a], %[b]\n\t" /* t0[63]=0 if same sign */
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"xor t1, %[a], %[res]\n\t" /* t1[63]=1 if sign changed */
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"not t0, t0\n\t" /* invert: same-sign -> MSB=1 */
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"and t0, t0, t1\n\t" /* both conditions met */
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"srli %[ovf], t0, 63\n\t" /* extract MSB as 0 or 1 */
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: [res]"=r"(res), [ovf]"=r"(ovf)
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: [a]"r"(a), [b]"r"(b)
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: "t0", "t1"
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);
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*result = res;
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return (int)ovf;
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}
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static inline int vm_sub_check_overflow(cell_t a, cell_t b, cell_t *result) {
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cell_t res;
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cell_t ovf;
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__asm__(
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"sub %[res], %[a], %[b]\n\t"
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/* Signed subtraction a-b overflows iff a and b have different signs
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* AND result has different sign from a:
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* ovf = (a XOR b)[63] AND (a XOR result)[63] */
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"xor t0, %[a], %[b]\n\t" /* t0[63]=1 if different sign */
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"xor t1, %[a], %[res]\n\t" /* t1[63]=1 if result sign differs */
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"and t0, t0, t1\n\t"
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"srli %[ovf], t0, 63\n\t"
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: [res]"=r"(res), [ovf]"=r"(ovf)
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: [a]"r"(a), [b]"r"(b)
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: "t0", "t1"
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);
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*result = res;
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return (int)ovf;
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}
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/* RV64M: mulh gives the high 64 bits of signed 64×64 product */
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static inline void vm_mul_double(cell_t a, cell_t b, cell_t *hi, cell_t *lo) {
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__asm__(
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"mul %[lo], %[a], %[b]\n\t" /* low 64 bits */
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"mulh %[hi], %[a], %[b]\n\t" /* high 64 bits (signed) */
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: [lo]"=r"(*lo), [hi]"=r"(*hi)
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: [a]"r"(a), [b]"r"(b)
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);
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}
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/* RV64M: div and rem */
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static inline void vm_divmod(cell_t dividend, cell_t divisor,
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cell_t *quotient, cell_t *remainder) {
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cell_t quot, rem;
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__asm__(
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"div %[quot], %[dividend], %[divisor]\n\t"
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"rem %[rem], %[dividend], %[divisor]\n\t"
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: [quot]"=r"(quot), [rem]"=r"(rem)
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: [dividend]"r"(dividend), [divisor]"r"(divisor)
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);
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*quotient = quot;
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*remainder = rem;
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}
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/* ============================================================================
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* OPTIMIZATION 3: String Operations
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* ============================================================================
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*
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* RISC-V has no string or SIMD instructions in the base ISA (rv64gc).
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* We write tight scalar loops in asm to avoid libc call overhead inside
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* the inner interpreter hot path.
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* ============================================================================
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*/
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static inline int vm_strcmp_asm(const char *s1, const char *s2, size_t len) {
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int result = 0;
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__asm__ __volatile__(
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"beqz %[len], 2f\n\t"
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"1:\n\t"
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"lb t0, 0(%[s1])\n\t"
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"lb t1, 0(%[s2])\n\t"
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"bne t0, t1, 3f\n\t"
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"addi %[s1], %[s1], 1\n\t"
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"addi %[s2], %[s2], 1\n\t"
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"addi %[len], %[len], -1\n\t"
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"bnez %[len], 1b\n\t"
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"2:\n\t"
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"mv %[res], zero\n\t"
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"j 4f\n\t"
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"3:\n\t"
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"li %[res], 1\n\t"
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"4:\n\t"
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: [res]"=r"(result),
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[s1]"+r"(s1), [s2]"+r"(s2), [len]"+r"(len)
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:
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: "t0", "t1", "memory"
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);
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return result;
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}
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static inline void vm_memcpy_asm(void *dest, const void *src, size_t len) {
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/* Copy 8 bytes at a time, then handle remainder */
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__asm__ __volatile__(
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"srli t2, %[len], 3\n\t" /* t2 = len / 8 */
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"beqz t2, 2f\n\t"
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"1:\n\t"
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"ld t0, 0(%[src])\n\t"
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"sd t0, 0(%[dst])\n\t"
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"addi %[src], %[src], 8\n\t"
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"addi %[dst], %[dst], 8\n\t"
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"addi t2, t2, -1\n\t"
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"bnez t2, 1b\n\t"
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"2:\n\t"
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"andi %[len], %[len], 7\n\t" /* remaining bytes */
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"beqz %[len], 4f\n\t"
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"3:\n\t"
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"lb t0, 0(%[src])\n\t"
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"sb t0, 0(%[dst])\n\t"
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"addi %[src], %[src], 1\n\t"
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"addi %[dst], %[dst], 1\n\t"
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"addi %[len], %[len], -1\n\t"
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"bnez %[len], 3b\n\t"
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"4:\n\t"
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: [src]"+r"(src), [dst]"+r"(dest), [len]"+r"(len)
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:
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: "t0", "t2", "memory"
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);
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}
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static inline void vm_memzero_asm(void *dest, size_t len) {
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__asm__ __volatile__(
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"srli t2, %[len], 3\n\t"
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"beqz t2, 2f\n\t"
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"1:\n\t"
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"sd zero, 0(%[dst])\n\t"
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"addi %[dst], %[dst], 8\n\t"
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"addi t2, t2, -1\n\t"
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"bnez t2, 1b\n\t"
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"2:\n\t"
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"andi %[len], %[len], 7\n\t"
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"beqz %[len], 4f\n\t"
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"3:\n\t"
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"sb zero, 0(%[dst])\n\t"
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"addi %[dst], %[dst], 1\n\t"
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"addi %[len], %[len], -1\n\t"
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"bnez %[len], 3b\n\t"
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"4:\n\t"
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: [dst]"+r"(dest), [len]"+r"(len)
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:
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: "t2", "memory"
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);
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}
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/* ============================================================================
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* OPTIMIZATION 4: Branchless Min/Max
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* ============================================================================
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*
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* RISC-V base ISA has no conditional move. The bit-mask trick avoids branches:
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* mask = -(a < b) → all-ones if a<b, zero otherwise
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* min = b + (a-b) & mask
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* ============================================================================
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*/
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static inline cell_t vm_min_asm(cell_t a, cell_t b) {
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cell_t result;
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__asm__(
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"slt t0, %[a], %[b]\n\t" /* t0 = (a < b) ? 1 : 0 */
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"neg t0, t0\n\t" /* t0 = mask (-1 or 0) */
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"sub t1, %[a], %[b]\n\t"
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"and t1, t1, t0\n\t"
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"add %[res], %[b], t1\n\t"
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: [res]"=r"(result)
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: [a]"r"(a), [b]"r"(b)
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: "t0", "t1"
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);
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return result;
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}
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static inline cell_t vm_max_asm(cell_t a, cell_t b) {
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cell_t result;
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__asm__(
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"slt t0, %[b], %[a]\n\t" /* t0 = (b < a) ? 1 : 0 → (a > b) */
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"neg t0, t0\n\t"
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"sub t1, %[a], %[b]\n\t"
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"and t1, t1, t0\n\t"
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"add %[res], %[b], t1\n\t"
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: [res]"=r"(result)
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: [a]"r"(a), [b]"r"(b)
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: "t0", "t1"
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);
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return result;
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}
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static inline cell_t vm_abs_asm(cell_t a) {
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cell_t result;
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__asm__(
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"srai t0, %[a], 63\n\t" /* t0 = sign mask (-1 or 0) */
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"xor %[res], %[a], t0\n\t" /* flip bits if negative */
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"sub %[res], %[res], t0\n\t" /* add 1 if negative (two's complement) */
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: [res]"=r"(result)
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: [a]"r"(a)
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: "t0"
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);
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return result;
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}
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/* ============================================================================
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* OPTIMIZATION 5: Bit Manipulation
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* ============================================================================
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*
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* rv64gc does NOT include the B extension (Zbb), so clz/ctz/cpop are not
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* available as single instructions. GCC builtins map to the best available
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* form — if the toolchain targets Zbb they'll lower to single instructions;
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* on plain rv64gc they fall back to efficient multi-instruction sequences.
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* ============================================================================
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*/
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static inline int vm_clz(cell_t x) {
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return __builtin_clzll((unsigned long long)x);
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}
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static inline int vm_ctz(cell_t x) {
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return __builtin_ctzll((unsigned long long)x);
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}
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static inline int vm_popcnt(cell_t x) {
|
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return __builtin_popcountll((unsigned long long)x);
|
||
}
|
||
|
||
/* ============================================================================
|
||
* OPTIMIZATION 6: Cache Operations
|
||
* ============================================================================
|
||
*
|
||
* RISC-V uses fence.i for instruction cache coherence.
|
||
* There is no user-space prefetch instruction in the base ISA;
|
||
* we use GCC's __builtin_prefetch which lowers to a hint if the target
|
||
* supports one (e.g., Zicbop extension), otherwise it's a no-op.
|
||
* ============================================================================
|
||
*/
|
||
|
||
static inline void vm_prefetch(const void *addr) {
|
||
__builtin_prefetch(addr, 0, 3);
|
||
}
|
||
|
||
static inline void vm_prefetch_stream(const void *addr) {
|
||
__builtin_prefetch(addr, 0, 0);
|
||
}
|
||
|
||
/* ============================================================================
|
||
* OPTIMIZATION 7: CPU Feature Detection
|
||
* ============================================================================
|
||
*
|
||
* RISC-V has no CPUID equivalent in user space. Extension detection requires
|
||
* either kernel support (/proc/cpuinfo, riscv_hwprobe syscall on Linux 6.4+)
|
||
* or compiler defines. We expose a simple interface here.
|
||
* ============================================================================
|
||
*/
|
||
|
||
static inline int vm_has_riscv_m_ext(void) {
|
||
#if defined(__riscv_mul)
|
||
return 1;
|
||
#else
|
||
return 0;
|
||
#endif
|
||
}
|
||
|
||
static inline int vm_has_riscv_b_ext(void) {
|
||
#if defined(__riscv_zbb)
|
||
return 1;
|
||
#else
|
||
return 0;
|
||
#endif
|
||
}
|
||
|
||
#else /* !USE_ASM_OPT */
|
||
|
||
#define vm_push_asm(vm, val) vm_push(vm, val)
|
||
#define vm_pop_asm(vm) vm_pop(vm)
|
||
#define vm_rpush_asm(vm, val) vm_rpush(vm, val)
|
||
#define vm_rpop_asm(vm) vm_rpop(vm)
|
||
|
||
#endif /* USE_ASM_OPT */
|
||
|
||
#endif /* VM_ASM_OPT_RISCV64_H */
|