Robert Allan JamesandClaude Sonnet 5
c54ea24aaf
Completes the CBW -> Data-In -> CSW chain for READ(10) started last commit. xhci_bot_read_data_in() and xhci_bot_receive_csw(), each a single Normal TRB on the bulk IN Transfer Ring via a new xhci_bulk_in_enqueue_and_ring() helper (mirrors the OUT-side helper from CBW send). All three stages now chain automatically via the existing deferred next_action pattern: CBW completion defers into Data-In, Data-In completion defers into CSW receive, CSW completion is where signature/tag/status validation happens. Data-In reads into a new fixed 512-byte bot_data_buf -- single-block scope for this increment, matches QEMU's usb-storage reported block size; xhci_bot_send_read10() now refuses rather than overflow/truncate if a request exceeds it. CSW validation (BOT spec section 5.2) checks dCSWSignature and dCSWTag (a new bot_last_tag field, latched from the CBW) before trusting bCSWStatus at all, so a garbled/misaligned CSW read can't be misread as a clean pass. usb_bot_csw_t follows the same struct-with-explicit-length-not-sizeof discipline as usb_bot_cbw_t. Verified live via a temporary probe (written, run once, log captured, reverted per this project's own probe convention), all three architectures, byte-identical: the full CBW -> Data-In -> CSW exchange completes cleanly, well-formed CSW with correct signature and echoed tag, no wedge, clean disconnect immediately after. The SCSI command itself reports CSW status FAILED against the current test fixture -- expected at this stage (no TEST UNIT READY / UNIT ATTENTION handling implemented yet, consistent with a fresh-attach unit-attention condition, not a transport-layer defect) and not root-caused further here; the BOT mechanism itself is confirmed correct end to end. Probe-free re-verification afterward on all three architectures. FABRIC-2.md Section X Milestone 2g's CSW checklist item marked done; "get one real READ(10) working end to end" stays explicitly open, distinguishing "the mechanism works" from "the SCSI command succeeds." Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01R4VMX6VSKCten8nGgaMkq4
476 lines
24 KiB
C
476 lines
24 KiB
C
/*
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* xhci_driver.h — xHCI USB host controller driver public API for StarKernel
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*
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* Register-layout definitions live in xhci.h; this header is the driver's
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* own state and public entry points, matching virtio_blk.h's split.
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*/
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#ifndef STARKERNEL_XHCI_DRIVER_H
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#define STARKERNEL_XHCI_DRIVER_H
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#include <stdint.h>
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#include "starkernel/pci.h"
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#include "starkernel/xhci.h"
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/* Driver state for one xHCI controller instance. Only one controller is
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* supported (matches virtio_blk's single-device precedent). */
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typedef struct {
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PciDevice pci;
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uint64_t bar0_phys; /* physical MMIO base, BAR0 */
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xhci_cap_regs_t *cap; /* BAR0 + 0 */
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xhci_op_regs_t *op; /* BAR0 + cap->cap_length */
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xhci_runtime_regs_t *runtime; /* BAR0 + cap->rts_off */
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xhci_doorbell_t *doorbell; /* BAR0 + cap->db_off */
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uint32_t max_slots;
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uint32_t max_ports;
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uint32_t max_intrs;
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uint32_t max_scratchpad_bufs;
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/* Set up by xhci_bringup(); NULL/0 until then. */
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void *dcbaa; /* Device Context Base Address Array */
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void *scratchpad_arr; /* array of scratchpad buffer pointers, if any */
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xhci_trb_t *cmd_ring; /* Command Ring, XHCI_RING_TRB_COUNT TRBs;
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* index XHCI_RING_TRB_COUNT-1 is a
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* permanent Link TRB back to index 0 */
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uint32_t cmd_ring_cycle; /* current Command Ring Cycle State (RCS) */
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uint32_t cmd_ring_enq; /* next free Command Ring index (0..COUNT-2) */
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xhci_trb_t *evt_ring; /* Event Ring, XHCI_RING_TRB_COUNT TRBs */
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void *evt_ring_seg_table; /* Event Ring Segment Table (1 entry) */
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uint32_t evt_ring_cycle; /* current Event Ring Cycle State */
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uint32_t evt_ring_deq; /* current Event Ring dequeue index */
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xhci_intr_regs_t *intr0; /* Interrupter 0 register set, cached
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* by xhci_bringup() for
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* xhci_poll_events() */
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/* Milestone 2e: connect -> Enable Slot correlation. port_slot_id is
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* indexed by port_id - 1 (1-based port IDs, matching PORTSC/Port
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* Status Change Event numbering); 0 means no slot allocated for that
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* port yet. Fixed-size, not heap-allocated -- XHCI_MAX_TRACKED_PORTS
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* comfortably covers any real or emulated root hub's port count
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* without adding a new kmalloc_aligned() call to xhci_bringup(); ports
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* beyond this bound (checked against both this array and max_ports)
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* are simply not tracked, matching this driver's existing preference
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* for fixed allocations over dynamic growth (xhci.h's own ring-sizing
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* rationale). Only one Enable Slot is ever in flight at a time (this
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* driver issues commands synchronously with respect to connect events,
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* not a queue) -- pending_connect_port_id is 0 when idle, or the
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* port_id whose Command Completion Event is still outstanding. */
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uint32_t port_slot_id[XHCI_MAX_TRACKED_PORTS];
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uint32_t pending_connect_port_id;
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uint32_t pending_connect_speed; /* PORTSC.Port Speed at connect time */
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/* Milestone 2e: Address Device. This driver only ever addresses one
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* device at a time (single-drive-at-a-time scope), so these are
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* single, reused allocations rather than per-slot -- lazily allocated
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* on the first connect that reaches xhci_cmd_address_device(), then
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* reinitialised (not reallocated) on every subsequent connect. connect
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* state tracks which command a still-outstanding completion event
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* belongs to, since Enable Slot and Address Device are issued
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* sequentially, not concurrently, for a given connect. */
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enum {
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XHCI_CONN_IDLE = 0,
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XHCI_CONN_AWAIT_ENABLE_SLOT,
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XHCI_CONN_AWAIT_ADDRESS_DEVICE,
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XHCI_CONN_AWAIT_DISABLE_SLOT,
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XHCI_CONN_AWAIT_CONFIGURE_ENDPOINT
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} connect_state;
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uint32_t pending_connect_slot_id;
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/* Milestone 2e/2g: disconnect teardown. Same single-outstanding-
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* command assumption as Enable Slot/Address Device above -- a
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* disconnect that arrives while another Command Ring command is
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* already outstanding is dropped rather than queued (matches the
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* existing "enable slot already pending -- dropped" precedent).
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* pending_disable_slot_id is captured at disconnect time, since the
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* port's own tracked slot ID (port_slot_id[]) is cleared immediately
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* on disconnect so a fresh connect on the same port isn't confused
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* for one already in progress -- by the time the Disable Slot
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* command's completion arrives, the port array no longer has it. */
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uint32_t pending_disable_slot_id;
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void *input_ctx; /* Input Control Ctx + Slot Ctx + EP0 Ctx (96 bytes, 32-byte contexts) */
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void *device_ctx; /* Slot Ctx + EP0 Ctx (64 bytes) -- DCBAA[slot_id] points here */
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xhci_trb_t *ep0_ring; /* EP0 Transfer Ring, XHCI_RING_TRB_COUNT TRBs */
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uint32_t ep0_ring_cycle;
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uint32_t ep0_ring_enq;
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/* Milestone 2f: EP0 control transfers. Like connect_state, this
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* driver only ever has one control transfer outstanding at a time --
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* pending_transfer_slot_id is 0 when idle, else the slot ID whose
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* Transfer Event (posted only by the Status Stage TRB, which alone
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* has IOC set) is still outstanding. transfer_purpose says which
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* request that is, since xhci_poll_events() needs to know which
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* buffer to interpret and what (if anything) to chain next on
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* success -- e.g. a successful short Configuration descriptor read
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* chains into a full-length read once wTotalLength is known.
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* device_descriptor is the full 18-byte standard USB device
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* descriptor; config_descriptor holds the Configuration descriptor
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* and everything after it in the same read (Interface + Endpoint
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* descriptors, concatenated, per USB spec) -- fixed 128 bytes,
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* comfortably covers a single-interface Mass Storage device's full
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* descriptor set without a dynamic allocation. All reused (not
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* per-slot), matching this driver's single-device scope. */
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enum {
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XHCI_XFER_NONE = 0,
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XHCI_XFER_DEVICE_DESC,
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XHCI_XFER_CONFIG_DESC_SHORT,
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XHCI_XFER_CONFIG_DESC_FULL,
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XHCI_XFER_SET_CONFIG,
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XHCI_XFER_CBW_SENT,
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XHCI_XFER_BOT_DATA_IN,
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XHCI_XFER_CSW_RECEIVED
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} transfer_purpose;
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uint32_t pending_transfer_slot_id;
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uint8_t device_descriptor[18];
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uint8_t config_descriptor[128];
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uint16_t config_total_length;
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/* Milestone 2g: bulk endpoints, discovered by walking the Endpoint
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* descriptors that follow the confirmed Mass Storage/BOT Interface
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* descriptor in config_descriptor. bEndpointAddress in full (not just
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* the endpoint number) -- bit 7 is needed later to pick the right
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* Doorbell target / EP Context DCI, and callers that want direction
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* alone can just mask it. 0 means "not found yet" for both --
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* endpoint address 0 is always EP0 (control), never a valid bulk
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* endpoint address, so it's a safe not-found sentinel. */
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uint8_t bulk_in_ep_addr;
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uint16_t bulk_in_max_packet;
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uint8_t bulk_out_ep_addr;
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uint16_t bulk_out_max_packet;
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/* Milestone 2g: bulk endpoint Transfer Rings, one per direction --
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* same fixed-ring-plus-Link-TRB pattern as ep0_ring, lazily allocated
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* once and reused across every connect (single-device scope, matching
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* every other ring in this driver). Not usable for actual transfers
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* until xhci_cmd_configure_endpoint() succeeds -- allocating them
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* early (rather than only after success) keeps the allocation site in
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* one place and lets the Input Context's EP Contexts point at real,
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* already-initialised rings before the command is even submitted. */
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xhci_trb_t *bulk_in_ring;
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uint32_t bulk_in_ring_cycle;
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uint32_t bulk_in_ring_enq;
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xhci_trb_t *bulk_out_ring;
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uint32_t bulk_out_ring_cycle;
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uint32_t bulk_out_ring_enq;
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/* Milestone 2g: Bulk-Only Transport. bot_cbw/bot_csw are reused across
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* every command (single-outstanding-transfer scope, matching every
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* other buffer in this driver) -- built/overwritten fresh each call,
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* not preserved between calls. bot_next_tag is a free-running counter
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* for dCBWTag; bot_last_tag latches the tag of the CBW currently in
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* flight, so the CSW stage can verify dCSWTag matches (BOT spec
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* requirement) without needing to re-derive it. bot_data_buf is a
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* fixed 512-byte Data-In destination -- covers exactly one 512-byte
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* block, this increment's whole scope (a real multi-block/variable-
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* block-size transfer is 2h's problem once the block subsystem
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* actually calls this path with real sizes). bot_expected_data_len is
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* the byte count the Data-In stage was told to read, staged at CBW
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* build time and consumed once the Data-In TRB is actually enqueued. */
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usb_bot_cbw_t bot_cbw;
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usb_bot_csw_t bot_csw;
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uint32_t bot_next_tag;
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uint32_t bot_last_tag;
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uint8_t bot_data_buf[512];
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uint32_t bot_expected_data_len;
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/* Deferred chaining: a doorbell ring (new control transfer) must
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* never happen synchronously from inside xhci_poll_events()'s event-
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* processing loop, before ERDP has been updated for the event
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* currently being handled -- confirmed live (amd64 QEMU) to hang the
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* guest outright when tried (a doorbell rung mid-acknowledgment of
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* the previous event, evidenced by checkpoint logging showing
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* execution stop exactly at the doorbell MMIO write). Chained
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* requests (device descriptor -> short config read -> full config
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* read) instead set these fields during event processing; the actual
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* doorbell ring happens once, after the main loop and the ERDP
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* write, from a small dispatch at the end of xhci_poll_events(). */
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enum {
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XHCI_NEXT_ACTION_NONE = 0,
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XHCI_NEXT_ACTION_GET_DEVICE_DESC,
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XHCI_NEXT_ACTION_GET_CONFIG_DESC,
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XHCI_NEXT_ACTION_CONFIGURE_ENDPOINT,
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XHCI_NEXT_ACTION_SET_CONFIG,
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XHCI_NEXT_ACTION_BOT_DATA_IN,
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XHCI_NEXT_ACTION_BOT_CSW_RECEIVE
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} next_action;
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uint32_t next_action_slot_id;
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uint16_t next_action_length;
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uint8_t next_action_config_value; /* SET_CONFIGURATION's wValue, staged by
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* the CONFIG_DESC_FULL handler once
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* bConfigurationValue is known */
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} xhci_dev_t;
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/*
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* xhci_find_and_map — locate the xHCI controller on PCI bus 0, enable it
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* (I/O+MEM+bus-master), map its BAR0 MMIO region, and
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* fill in the four register-region pointers in *dev.
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*
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* dev must point to a zero-initialised xhci_dev_t.
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*
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* Returns 0 on success.
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* Returns -1 if no xHCI device was found on the PCI bus.
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* Returns -2 if the BAR0 mapping failed.
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*/
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int xhci_find_and_map(xhci_dev_t *dev);
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/*
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* xhci_bringup — reset the controller, allocate and program the DCBAA,
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* Command Ring, and Event Ring (Interrupter 0), then start
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* the controller (RUN/STOP=1) and confirm it left the
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* halted state.
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*
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* Must be called after a successful xhci_find_and_map(). Does not enable
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* interrupts (USBCMD.INTE / IMAN.IE) -- this driver is polled, not
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* interrupt-driven (see xhci_poll_events()'s own doc comment for why).
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*
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* Returns 0 on success.
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* Returns -1 on reset timeout.
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* Returns -2 on allocation failure.
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* Returns -3 if the controller failed to leave the halted state after RUN.
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* On success, latches dev into the module-static pointer xhci_poll_events()
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* reads -- only one controller is supported, matching virtio_blk's
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* single-device precedent.
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*/
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int xhci_bringup(xhci_dev_t *dev);
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/*
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* xhci_poll_events — read Interrupter 0's Event Ring, dispatching each TRB
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* by type: Port Status Change reads PORTSC to log
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* connect/disconnect and acknowledges CSC; Command
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* Completion and Transfer Event are logged only (slot
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* allocation and BOT transfers are later increments).
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* Advances the Event Ring dequeue pointer and clears
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* ERDP.EHB when done.
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*
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* Polled, not interrupt-driven: an initial attempt at IRQ delivery
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* (Milestone 2d's first draft) found the amd64 PCI INTx routing formula
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* gives a demonstrably wrong GSI (checked live via QMP query-pci: xHCI at
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* PCI slot 4 reports IRQ 10, the formula predicted 16), and the
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* aarch64/riscv64 slot/pin-derived source IDs were unverified at the new
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* slot this controller occupies. Rather than guess further at chipset
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* PIRQ routing, this matches Section U item 6's own design intent
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* (Captain Bob: "interrupt-driven, coarse cadence, cheap early-exit...
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* quick check blocks... done") via sk_repl_idle()'s existing coarse-cadence
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* hook instead of a per-arch IRQ path -- USB insertion is a human-timescale
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* event, not a hot path, so polling costs nothing meaningful here.
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*
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* No arguments and no return value -- only one xHCI controller is
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* supported, so the caller needs no device handle. A no-op if
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* xhci_bringup() has not completed successfully (dev pointer not yet
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* latched).
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*/
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void xhci_poll_events(void);
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/*
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* xhci_cmd_enable_slot — submit an Enable Slot command TRB to the Command
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* Ring and ring doorbell 0. Does not wait for or
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* read the resulting Command Completion Event -- it
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* arrives asynchronously via xhci_poll_events(),
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* which correlates the returned Slot ID back to
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* dev->pending_connect_port_id and records it in
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* dev->port_slot_id[].
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*
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* Called from xhci_poll_events()'s own Port Status Change handling on a
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* real connect event -- not called directly by other code.
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*
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* Returns 0 if the command was posted, -1 if dev/dev->cmd_ring is not set
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* up (xhci_bringup() has not completed).
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*/
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int xhci_cmd_enable_slot(xhci_dev_t *dev);
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/*
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* xhci_cmd_disable_slot — submit a Disable Slot command TRB for slot_id
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* and ring doorbell 0. Does not wait for or read
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* the resulting Command Completion Event -- it
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* arrives asynchronously via xhci_poll_events(),
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* which clears DCBAA[slot_id] on success.
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*
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* Called from xhci_poll_events()'s own Port Status Change handling on a
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* real disconnect event, for a slot that was actually addressed -- not
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* called directly by other code.
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*
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* Returns 0 if the command was posted, -1 if dev/dev->cmd_ring is not set
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* up.
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*/
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int xhci_cmd_disable_slot(xhci_dev_t *dev, uint32_t slot_id);
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/*
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* xhci_cmd_address_device — build the Input Context (Slot + EP0, add-only),
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* program DCBAA[slot_id] with the Device Context,
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* allocate the EP0 Transfer Ring, and submit an
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* Address Device command TRB.
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*
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* speed is the PORTSC.Port Speed value read live at the connect this call
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* is servicing (xHCI 1.2 spec table 7-13 speed IDs) -- used to pick EP0's
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* default Max Packet Size before any device descriptor has been read.
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*
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* Refuses (-2) if HCCPARAMS1.CSZ indicates 64-byte contexts -- only
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* 32-byte contexts are implemented (see xhci.h's own doc comment on
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* xhci_slot_ctx32_t).
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*
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* Called from xhci_poll_events()'s Command Completion handling once Enable
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* Slot succeeds -- not called directly by other code.
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*
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* Returns 0 if the command was posted, -1 on allocation failure, -2 if
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* 64-byte contexts are required.
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*/
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int xhci_cmd_address_device(xhci_dev_t *dev, uint32_t slot_id,
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uint32_t port_id, uint32_t speed);
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/*
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* xhci_cmd_configure_endpoint — build the Input Context (Slot + the two
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* bulk EP Contexts, add-only), allocate the
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* bulk Transfer Rings, and submit a
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* Configure Endpoint command TRB for
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* slot_id.
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*
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* Per xHCI 1.2 spec section 4.3.5, this must be issued after enumeration
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* has identified the endpoints a device's chosen configuration/interface
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* actually uses, and before the USB SET_CONFIGURATION request is sent to
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* the device -- the reverse of that order (which this driver used before
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* this increment) works against QEMU's lenient emulation but is not
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* spec-correct. Requires dev->bulk_in_ep_addr/bulk_out_ep_addr to already
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* be populated (2f's config descriptor walk) -- refuses if either is
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* still 0 (not found).
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*
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* The Slot Context's Route String/Speed/Root Hub Port/Interrupter Target
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* fields are copied from the already-addressed device's own Device
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* Context (populated by a prior successful Address Device) rather than
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* reconstructed from scratch -- those values aren't retained anywhere
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* else by the time enumeration reaches this point (pending_connect_port_id
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* is cleared as soon as Address Device completes). Only Context Entries is
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* changed, to the highest DCI now in use.
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*
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* Called from xhci_poll_events()'s deferred next_action dispatch once the
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* full Configuration descriptor has confirmed a Mass Storage/BOT interface
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* and identified both bulk endpoints -- not called directly by other code.
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*
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* Returns 0 if the command was posted, -1 on allocation failure or missing
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* prerequisite state, -2 if 64-byte contexts are required.
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*/
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int xhci_cmd_configure_endpoint(xhci_dev_t *dev, uint32_t slot_id);
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/*
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* xhci_bot_send_read10 — build a Command Block Wrapper for a SCSI
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* READ(10) and submit it on the bulk OUT Transfer
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* Ring; the Data-In stage and CSW receive follow
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* automatically once this CBW's own completion
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* arrives (see xhci_bot_read_data_in()/
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* xhci_bot_receive_csw() below), same deferred-
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* chaining pattern as device descriptor -> config
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* descriptor -> Configure Endpoint -> SET_CONFIG.
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*
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* lba is the starting Logical Block Address, num_blocks the SCSI transfer
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* length (blocks, not bytes -- READ(10)'s own field), block_size the
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* device's actual bytes-per-block, used only to compute
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* dCBWDataTransferLength (the data stage's total byte length CBW
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* declares up front, not carried in the CDB itself). num_blocks*block_size
|
|
* must fit in dev->bot_data_buf (512 bytes, this increment's whole scope
|
|
* -- see xhci_dev_t's own doc comment) -- refuses otherwise.
|
|
*
|
|
* Does not wait for or read any of the three stages' Transfer Events --
|
|
* they arrive asynchronously via xhci_poll_events(), correlated via
|
|
* dev->transfer_purpose, same pattern as every other transfer in this
|
|
* driver. The final result (CSW signature/tag/status validated) is only
|
|
* ever logged, not returned to any caller -- there is no synchronous
|
|
* "did the read succeed" API yet; that's 2h's problem once something
|
|
* actually needs the data back.
|
|
*
|
|
* Requires bulk_out_ep_addr/bulk_out_ring and bulk_in_ep_addr/
|
|
* bulk_in_ring to already be populated (2f/2g's config descriptor walk
|
|
* and Configure Endpoint command) -- refuses if any prerequisite is
|
|
* missing.
|
|
*
|
|
* Returns 0 if the CBW was posted, -1 if a prerequisite is missing or
|
|
* the requested transfer size exceeds dev->bot_data_buf.
|
|
*/
|
|
int xhci_bot_send_read10(xhci_dev_t *dev, uint32_t slot_id, uint32_t lba,
|
|
uint16_t num_blocks, uint32_t block_size);
|
|
|
|
/*
|
|
* xhci_bot_read_data_in — submit a Normal TRB on the bulk IN Transfer
|
|
* Ring to read dev->bot_expected_data_len bytes
|
|
* into dev->bot_data_buf.
|
|
*
|
|
* Called from xhci_poll_events()'s deferred next_action dispatch once a
|
|
* CBW's own Command completion (XHCI_XFER_CBW_SENT) succeeds -- not
|
|
* called directly by other code.
|
|
*
|
|
* Returns 0 if the TRB was posted, -1 if bulk_in_ring isn't set up.
|
|
*/
|
|
int xhci_bot_read_data_in(xhci_dev_t *dev, uint32_t slot_id);
|
|
|
|
/*
|
|
* xhci_bot_receive_csw — submit a Normal TRB on the bulk IN Transfer Ring
|
|
* to read the 13-byte Command Status Wrapper into
|
|
* dev->bot_csw.
|
|
*
|
|
* Called from xhci_poll_events()'s deferred next_action dispatch once the
|
|
* Data-In stage's own Transfer Event (XHCI_XFER_BOT_DATA_IN) succeeds --
|
|
* not called directly by other code. The CSW's own completion
|
|
* (XHCI_XFER_CSW_RECEIVED) is where signature/tag/status validation
|
|
* against dev->bot_last_tag actually happens, in xhci_poll_events()
|
|
* itself, not here.
|
|
*
|
|
* Returns 0 if the TRB was posted, -1 if bulk_in_ring isn't set up.
|
|
*/
|
|
int xhci_bot_receive_csw(xhci_dev_t *dev, uint32_t slot_id);
|
|
|
|
/*
|
|
* xhci_ep0_get_device_descriptor — issue a standard GET_DESCRIPTOR
|
|
* (Device) control transfer (Setup +
|
|
* Data-IN + Status-OUT stages) on
|
|
* slot_id's EP0, reading the 18-byte
|
|
* result into dev->device_descriptor.
|
|
* Sets dev->transfer_purpose so
|
|
* xhci_poll_events() knows how to
|
|
* interpret the completion.
|
|
*
|
|
* Called once Address Device succeeds -- not called directly by other
|
|
* code.
|
|
*
|
|
* Returns 0 if the transfer was posted, -1 if dev/dev->ep0_ring is not
|
|
* set up.
|
|
*/
|
|
int xhci_ep0_get_device_descriptor(xhci_dev_t *dev, uint32_t slot_id);
|
|
|
|
/*
|
|
* xhci_ep0_get_config_descriptor — issue a GET_DESCRIPTOR (Configuration)
|
|
* control transfer for `length` bytes,
|
|
* reading into dev->config_descriptor
|
|
* (capped to its fixed size). Used
|
|
* twice per device: once for a short
|
|
* 9-byte read (just the Configuration
|
|
* descriptor header, to learn
|
|
* wTotalLength) and once for the full
|
|
* read once that length is known --
|
|
* xhci_poll_events() chains the second
|
|
* call automatically on the first
|
|
* read's success.
|
|
*
|
|
* Called once the device descriptor read succeeds -- not called directly
|
|
* by other code.
|
|
*
|
|
* Returns 0 if the transfer was posted, -1 if dev/dev->ep0_ring is not
|
|
* set up.
|
|
*/
|
|
int xhci_ep0_get_config_descriptor(xhci_dev_t *dev, uint32_t slot_id, uint16_t length);
|
|
|
|
/*
|
|
* xhci_ep0_set_configuration — issue a SET_CONFIGURATION control transfer
|
|
* (Setup + Status stage only, no Data stage)
|
|
* with wValue = config_value. Moves the
|
|
* device from Addressed into Configured
|
|
* state -- required before any endpoint
|
|
* other than EP0 (i.e. the bulk IN/OUT
|
|
* endpoints 2g needs) can be used.
|
|
*
|
|
* Called once the Configuration descriptor read confirms a Mass Storage/
|
|
* SCSI/BOT device, with config_value = that descriptor's own
|
|
* bConfigurationValue field -- not called directly by other code.
|
|
*
|
|
* Returns 0 if the transfer was posted, -1 if dev/dev->ep0_ring is not
|
|
* set up.
|
|
*/
|
|
int xhci_ep0_set_configuration(xhci_dev_t *dev, uint32_t slot_id, uint8_t config_value);
|
|
|
|
#endif /* STARKERNEL_XHCI_DRIVER_H */
|