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FABRIC.md: aarch64 keyboard punch list -- GIC-SPI derivation, no landmine

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Live-probed GICD_ITARGETSR before starting 4.3.5d/e; survived cleanly,
unlike riscv64's PLIC (4.3.5a). Decoded QEMU's own virt DTB for the PCI
slot->SPI interrupt-map routing table and closed-form formula. Amended
4.3.5d's circular acceptance criterion to a synthetic GICD_ISPENDR probe
(mirrors 4.3.5b's fix for the same problem), and wrote the full 4.3.5e
virtio-input execution plan: device ID 0x1052, the real virtio_input_event
struct, the mandatory ISR-status read, and the pci_enable() interrupt-
disable-bit gap.

Log: logs/20260808-093228/aarch64/.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
This commit is contained in:
Robert Allan James
2026-08-08 09:56:20 -04:00
co-authored by Claude Sonnet 5
parent e01c4e33e4
commit 06283e5364
6 changed files with 18375 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files
FABRIC.md
+152 -4
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@@ -3978,18 +3978,120 @@ document and committing that amendment as its own item.*
registers) that today's minimal init never touches. This item extends the GIC init from
0.6 just far enough to enable and route one SPI, still not a general driver — scope stays
as narrow as 0.6's did.
*Done when:* aarch64 can take and acknowledge (`IAR`/`EOIR`) an SPI from the virtio-input
PCI device, three-arch QEMU boot unaffected, log committed.
**Amended 2026-08-08 — original acceptance was circular.** "Take and acknowledge an SPI
from the virtio-input PCI device" can't close as its own commit: that device doesn't
exist until 4.3.5e, so this item could never be verified in isolation, breaking §25.0's
one-item-one-commit rule. Fixed the same way 4.3.5b already fixed the identical problem
for the PLIC — verify against a **synthetic/known** interrupt, not the real device.
Concrete steps:
1. Add `PCI_CFG_INT_PIN` (offset `0x3D`, byte — the Interrupt Pin register) to
`include/starkernel/pci.h`, alongside the existing `PCI_CFG_INT_LINE` (`0x3C`).
2. Compute the target SPI at **runtime**, not a hardcoded constant:
`pin = pci_read8(dev, PCI_CFG_INT_PIN)` (1=INTA…4=INTD), `slot = dev->device`
(already populated by `pci_find_first()`), `spi = 3 + ((slot + pin - 1) % 4)` →
INTID `32 + spi`. Derived live from this host's QEMU 10.2.1 `virt` DTB, not recalled
— full decode and the table it produced are in §27.5.
3. Program, for the computed `intid`: `GICD_IPRIORITYR` at `0x400 + intid` (value `0x80`,
matching `TIMER_PRIORITY`); `GICD_ISENABLER` at `0x100 + 4*(intid/32)` (`0x104` for
every candidate INTID 35–38), bit `intid % 32`; `GICD_ITARGETSR` at `0x800 + intid`
(`0x823`–`0x826`), value `0x01` (single vCPU — this target has no `-smp`). `GICD_ICFGR`:
read back first; §27.5's decode says this SPI should already default level-triggered,
write only if the readback disagrees — keep item 0.6's "don't touch ICFGR unless
forced to" posture.
4. Verify with **no device present**: software-pend the computed SPI via `GICD_ISPENDR`
(offset `0x200 + 4*(intid/32)`, bit `intid % 32` — standard GICv2 architecture
register, ARM IHI 0048B), confirm it is taken, read via `GICC_IAR`, and completed via
`GICC_EOIR` through `aarch64_irq_handler()`. This is the actual acceptance below.
*Done when:* a software-pended SPI (via `GICD_ISPENDR`, no device present) on the
computed target INTID is taken and acknowledged (`IAR`/`EOIR`), three-arch QEMU boot
unaffected, log committed.
*Refs:* §27.5.
> **Scoping check, 2026-08-08 — no landmine found (unlike 4.3.5a).** Before starting this
> item, checked whether aarch64 carries the same class of gap that blocked riscv64:
> `arch_mmu_init()` (`arch/aarch64/arch.c:169`) is an identical stub — "page-table setup...
> deferred to a later milestone" — so aarch64's MMIO likewise depends entirely on whatever
> EDK2 left mapped at `ExitBootServices()`, an assumption `apic.c`'s own header comment
> (lines 76–79) already names. Live-tested rather than inferred, same rigor as 4.3.5a's
> discovery: added a temporary probe (read-modify-write to `GICD_ITARGETSR[32]`, offset
> `0x820`) immediately after 0.6's existing `GICD_CTLR`/`ISENABLER0`/`IPRIORITYR` writes,
> booted aarch64 alone in QEMU. Result: survived — `GICv2 probe: ITARGETSR[32] read+write
> survived` printed, boot proceeded clean to `ok>`, no exception (log:
> `logs/20260808-093228/aarch64/`). `0x820` isn't itself one of this item's real targets —
> those, per the DTB decode above, are INTID 35–38 at `0x823`–`0x826` — but all of them sit
> in the same 4KB page as `0x820` and as the offsets item 0.6 already proves reachable on
> every boot (`0x000`/`0x100`/`0x400`), so the probe validates the page, not a coincidence.
> Unlike riscv64's PLIC threshold register, which sat 2MB deep in a part of its MMIO window
> nothing had ever touched, that page-adjacency is why this item doesn't carry a
> 4.3.5a-shaped prerequisite. 4.3.5e's PCI-BAR MMIO transport is likewise already proven
> live (`virtio-blk-pci` uses it today on this same board). Probe code reverted after
> recording this result — not committed; this item remains unstarted.
- [ ] **4.3.5e — aarch64: virtio-keyboard-pci, interrupt-driven.** Add `virtio-keyboard-pci`
to the aarch64 `qemu`/`qemu-esp` targets — the existing `virtio-blk-pci` device proves the
PCI bus is already enumerated (`pci.c`) on this board, so this rides the same bus, a new
device class. Same virtio-input driver shape as 4.3.5c (shared code where the transport
allows — MMIO vs. PCI config-space discovery differs, the event-queue/`EV_KEY` decode
should not). Built on 4.3.5d.
*Done when:* a keypress in QEMU on aarch64 produces a captured `EV_KEY` event via the
interrupt path with no polling loop, three-arch QEMU boot unaffected, log committed.
Concrete steps:
1. Add `-device virtio-keyboard-pci` to the aarch64 `qemu`/`qemu-esp` targets in
`Makefile.starkernel`. Confirmed available in this host's QEMU 10.2.1
(`qemu-system-aarch64 -device help` lists it, bus PCI, alias `virtio-keyboard`).
2. New `include/starkernel/virtio_input.h` / `src/starkernel/virtio/virtio_input.c`.
Device identity: vendor `0x1AF4` (same as blk), device ID `0x1052` — the modern-ID
formula `0x1040 + VIRTIO_ID_INPUT`, `VIRTIO_ID_INPUT = 18` per this build host's
`/usr/include/linux/virtio_ids.h`. No legacy/transitional ID exists for virtio-input
(unlike blk's `0x1001` fallback — input postdates the legacy 0.9.5 spec), so
`pci_find_first()` only needs the one modern ID, no fallback branch.
3. Event structure, from this host's `/usr/include/linux/virtio_input.h` and
`/usr/include/linux/input-event-codes.h` (authoritative, not recalled): `struct
virtio_input_event { __le16 type; __le16 code; __le32 value; }` (8 bytes), `EV_KEY =
0x01`.
4. **Design decision, flagged not resolved here:** `walk_virtio_caps()` (the
capability-list walker `virtio_blk.c` uses for `COMMON_CFG`/`NOTIFY_CFG`) is `static`
inside that file. This item needs the same walk plus, new, `ISR_CFG` (step 6). Promote
it to a shared `virtio_pci.c`/`.h`, or duplicate it here? Get a ruling before writing
code — don't default to one silently (§25.0 rule 3).
5. `pci_enable()` (`pci.c:363`) sets only IO/MEM/BUS_MASTER in the PCI COMMAND register —
it never clears bit 10 (Interrupt Disable). If that bit is set at enumeration, INTx
never asserts and every earlier step passes while producing zero real interrupts —
same failure shape as 4.3.5's OVMF-scanning-disabled bug (finding 2 in that item's done
note). Read COMMAND back after `pci_enable()` and confirm/clear bit 10.
6. Device init follows `vblk_init_device()`'s sequence (`virtio_blk.c:361-499`) almost
exactly — reset → ACKNOWLEDGE → DRIVER → negotiate `VIRTIO_F_VERSION_1` → FEATURES_OK →
configure queue(s) → DRIVER_OK. Differences:
- Two virtqueues (eventq index 0, statusq index 1) — read `common->num_queues` back
from the device rather than hardcoding 2, same live-verification discipline as
everything else in this item.
- Unlike `vblk_io()`'s request/response pattern, the driver pre-posts N empty
`virtio_input_event` buffers (device-writable) into the eventq's avail ring at init
and does not wait synchronously — the device fills and posts a buffer to the used
ring asynchronously, signalled by the interrupt wired in 4.3.5d, not a poll loop.
Buffers must be re-posted after being drained in the ISR.
- statusq (index 1) is for driver→device reports (LED state) — not needed to read
keypresses; configure it (spec expects both queues set up) but leave it unused.
- **New for this tree, mandatory:** `virtio_blk.c` defines `VIRTIO_PCI_CAP_ISR_CFG = 3`
but never reads it — `vblk_io()` polls and never handles a real interrupt, so it
never needed to. This item is the first interrupt-driven virtio-pci device here.
Because the routed SPI is level-triggered (§27.5's decoded `interrupt-map` flags =
`0x4`), the ISR handler **must** read the ISR-status capability byte
(`walk_virtio_caps(pci, VIRTIO_PCI_CAP_ISR_CFG, NULL)`) — that read is what
deasserts the line. Skipping it leaves INTx asserted after the first event: an
interrupt storm or a permanent hang, not a subtle bug.
- Report, don't fix: `virtio_blk.c`'s `wmb()`/`rmb()` (`virtio_blk.c:221-226`) are
compiler barriers only (`asm volatile("" ::: "memory")`), no real memory fence.
Adequate for blk's synchronous polled loop; an interrupt-driven used-ring (device
writes concurrently with the driver's re-post loop) leans on this ordering harder.
Not this item's job to fix tree-wide — report if it manifests as a live symptom.
*Done when:* a keypress in QEMU on aarch64 (via `sendkey`, same manual-injection
technique as 4.3.5's amd64 verification) produces a captured `EV_KEY` event through the
interrupt path with no polling loop anywhere in the path, three-arch QEMU boot
unaffected, log committed.
*Refs:* §27.5.
- [ ] **4.3.5f — Checkpoint: one keyboard abstraction, three architectures, no polling.**
@@ -4429,3 +4531,49 @@ index, which would have been the fast/wrong way to get a key on screen quickly.
4.3.5f is the checkpoint, same posture as 4.3.4: converge the three architecture-specific
paths behind one interface before anything scopes REPL line input on top of it.
### 27.5.1 aarch64 GIC-SPI derivation for 4.3.5d/4.3.5e (2026-08-08)
Two facts 4.3.5d/4.3.5e depend on were derived live rather than assumed, same discipline as
`apic.c`'s own file header uses for the timer PPI values (item 0.6).
**1. aarch64 has no 4.3.5a-shaped landmine.** `arch_mmu_init()` (`arch/aarch64/arch.c:169`)
is the same kind of stub as riscv64's Sv39 gap — MMU bring-up "deferred to a later
milestone" — so aarch64's MMIO also depends entirely on whatever EDK2 left mapped at
`ExitBootServices()`. Live-probed rather than inferred: a temporary read-modify-write to
`GICD_ITARGETSR` (offset `0x820`, within the same 4KB page as this item's real target
offsets `0x823`–`0x826`) survived cleanly on a solo aarch64 boot — no exception, boot
proceeded to `ok>` (log: `logs/20260808-093228/aarch64/`). Recorded at the 4.3.5d entry
itself (§25.5); this subsection is the supporting derivation, not a duplicate record.
**2. The PCI slot→SPI routing formula, decoded from QEMU's own DTB, not recalled.**
Dumped with `qemu-system-aarch64 -machine virt,dumpdtb=<file> -cpu cortex-a57` (QEMU
10.2.1, the exact binary and machine/cpu flags this tree's `qemu` target uses —
`Makefile.starkernel:822-824`) and decoded by hand-parsing the FDT struct block (no `dtc`
installed on this build host) for the `pcie@10000000` node's `interrupt-map` /
`interrupt-map-mask` properties. `interrupt-map-mask` = `0x1800 0 0 0x7` masks PCI device
number down to its low 2 bits (`slot mod 4`) and the full 3-bit INTx pin field — meaning
the table's 16 explicit entries (slots 0–3 × INTA–D) cover **every** PCI slot QEMU assigns,
not just 0–3, because routing repeats every 4 slots. Decoded table (INTID = GIC SPI number
+ 32; flags `0x4` = `IRQ_TYPE_LEVEL_HIGH` throughout):
| slot mod 4 | INTA | INTB | INTC | INTD |
|---|---|---|---|---|
| 0 | INTID 35 (SPI 3) | INTID 36 (SPI 4) | INTID 37 (SPI 5) | INTID 38 (SPI 6) |
| 1 | INTID 36 (SPI 4) | INTID 37 (SPI 5) | INTID 38 (SPI 6) | INTID 35 (SPI 3) |
| 2 | INTID 37 (SPI 5) | INTID 38 (SPI 6) | INTID 35 (SPI 3) | INTID 36 (SPI 4) |
| 3 | INTID 38 (SPI 6) | INTID 35 (SPI 3) | INTID 36 (SPI 4) | INTID 37 (SPI 5) |
Closed form, used at runtime by 4.3.5d/e rather than a hardcoded constant (the aarch64
`qemu`/`qemu-esp` targets don't pin PCI slot addresses the way the riscv64 target's
`addr=0x1`/`addr=0x2` do, so the keyboard's slot is whatever QEMU assigns):
```
pin = pci_read8(dev, PCI_CFG_INT_PIN) /* config offset 0x3D; 1=INTA .. 4=INTD */
slot = dev->device /* already populated by pci_find_first() */
spi = 3 + ((slot + pin - 1) % 4)
intid = 32 + spi /* 35..38 */
```
Not yet decoded/needed: entries for PCI bridge-forwarded interrupts or multi-function
devices beyond function 0 — out of scope for a single virtio-keyboard-pci device on bus 0.
capsules/BLOCK_MAP.md
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@@ -1,5 +1,5 @@
# Capsule Block Manifest — Auto-generated
<!-- Generated by mkcapsule --manifest 2026-08-08T04:16:22Z -->
<!-- Generated by mkcapsule --manifest 2026-08-08T13:32:17Z -->
<!-- DO NOT EDIT — re-run mkcapsule --manifest to refresh. -->
<!-- Hand-written justifications and immutability notes live -->
<!-- in MANIFEST.md alongside this auto-generated index. -->
disk/artemis.img
BIN
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experiments/bare_metal/latest/aarch64.csv
+11 -11
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@@ -57,7 +57,7 @@ tick_number,elapsed_ns,tick_interval_ns,cache_hits_delta,bucket_hits_delta,word_
56,560000,10000,0,0,211,103,32,4096,1620,0,0,0,65536,0,0,65536,0,0
57,570000,10000,0,0,193,110,33,4096,1712,0,0,0,65536,0,0,65536,0,0
58,580000,10000,0,0,190,5,67,4096,1775,0,0,0,65536,0,0,65536,0,0
1,10000,18446744073708981616,0,0,117,4,4,4096,0,0,4895412794951728869,9,65536,0,0,65536,0,0
1,10000,18446744073708981616,0,0,117,4,4,4096,0,0,4895412794951728869,10,65536,0,0,65536,0,0
2,20000,10000,0,0,78,10,7,4096,0,0,0,11,65536,0,0,65536,0,0
3,30000,10000,0,0,101,13,7,4096,0,0,0,12,65536,0,0,65536,0,0
4,40000,10000,0,0,63,19,8,4096,0,0,0,13,65536,0,0,65536,0,0
@@ -66,9 +66,9 @@ tick_number,elapsed_ns,tick_interval_ns,cache_hits_delta,bucket_hits_delta,word_
7,70000,10000,0,0,228,32,8,4096,210,0,0,22,65536,0,0,65536,0,0
8,80000,10000,0,0,256,34,9,4096,466,0,0,29,65536,0,0,65536,0,0
9,90000,10000,0,0,256,36,10,4096,722,0,0,35,65536,0,0,65536,0,0
10,100000,10000,0,0,256,36,11,4096,978,0,0,41,65536,0,0,65536,0,0
10,100000,10000,0,0,256,36,11,4096,978,0,0,42,65536,0,0,65536,0,0
11,110000,10000,0,0,256,36,11,4096,1234,0,0,48,65536,0,0,65536,0,0
12,120000,10000,0,0,256,36,12,4096,1490,0,0,54,65536,0,0,65536,0,0
12,120000,10000,0,0,256,36,12,4096,1490,0,0,55,65536,0,0,65536,0,0
13,130000,10000,0,0,256,37,12,4096,1746,0,0,61,65536,0,0,65536,0,0
14,140000,10000,0,0,230,39,12,4096,1949,0,0,67,65536,0,0,65536,0,0
15,150000,10000,0,0,256,39,13,4096,2204,0,0,73,65536,0,0,65536,0,0
@@ -84,12 +84,12 @@ tick_number,elapsed_ns,tick_interval_ns,cache_hits_delta,bucket_hits_delta,word_
25,250000,10000,0,0,256,43,20,2048,2048,0,0,140,65536,0,1,65536,0,0
26,260000,10000,0,0,256,45,21,2048,2048,0,0,147,65536,0,1,65536,0,0
27,270000,10000,0,0,256,45,22,1024,1024,0,0,153,65536,0,1,65536,0,0
28,280000,10000,0,0,256,45,23,1024,1024,0,0,160,65536,0,1,65536,0,0
28,280000,10000,0,0,256,45,23,1024,1024,0,0,159,65536,0,1,65536,0,0
29,290000,10000,0,0,256,45,24,512,512,0,0,166,65536,0,1,65536,0,0
30,300000,10000,0,0,256,45,24,512,512,0,0,173,65536,0,1,65536,0,0
31,310000,10000,0,0,256,45,25,256,256,0,0,180,65536,0,1,65536,0,0
32,320000,10000,0,0,255,45,26,256,256,0,0,186,65536,0,1,65536,0,0
33,330000,10000,0,0,256,45,27,256,256,0,0,193,65536,0,1,65536,0,0
34,340000,10000,0,0,256,45,27,256,256,0,0,199,65536,0,1,65536,0,0
35,350000,10000,0,0,256,45,28,256,256,0,0,207,65536,0,1,65536,0,0
36,360000,10000,0,0,256,45,29,256,256,0,0,221,65536,0,1,65536,0,0
30,300000,10000,0,0,256,45,24,512,512,0,0,172,65536,0,1,65536,0,0
31,310000,10000,0,0,256,45,25,256,256,0,0,179,65536,0,1,65536,0,0
32,320000,10000,0,0,255,45,26,256,256,0,0,185,65536,0,1,65536,0,0
33,330000,10000,0,0,256,45,27,256,256,0,0,192,65536,0,1,65536,0,0
34,340000,10000,0,0,256,45,27,256,256,0,0,198,65536,0,1,65536,0,0
35,350000,10000,0,0,256,45,28,256,256,0,0,205,65536,0,1,65536,0,0
36,360000,10000,0,0,256,45,29,256,256,0,0,211,65536,0,1,65536,0,0
1 tick_number elapsed_ns tick_interval_ns cache_hits_delta bucket_hits_delta word_executions_delta hot_word_count avg_word_heat_q48 window_width actual_window_size predicted_label_hits jitter_bits apic_ticks time_trust_q48 variance_q48 vm_call_depth_max hera_heat_q48 hermes_heat_q48 artemis_heat_q48
57 56 560000 10000 0 0 211 103 32 4096 1620 0 0 0 65536 0 0 65536 0 0
58 57 570000 10000 0 0 193 110 33 4096 1712 0 0 0 65536 0 0 65536 0 0
59 58 580000 10000 0 0 190 5 67 4096 1775 0 0 0 65536 0 0 65536 0 0
60 1 10000 18446744073708981616 0 0 117 4 4 4096 0 0 4895412794951728869 9 10 65536 0 0 65536 0 0
61 2 20000 10000 0 0 78 10 7 4096 0 0 0 11 65536 0 0 65536 0 0
62 3 30000 10000 0 0 101 13 7 4096 0 0 0 12 65536 0 0 65536 0 0
63 4 40000 10000 0 0 63 19 8 4096 0 0 0 13 65536 0 0 65536 0 0
66 7 70000 10000 0 0 228 32 8 4096 210 0 0 22 65536 0 0 65536 0 0
67 8 80000 10000 0 0 256 34 9 4096 466 0 0 29 65536 0 0 65536 0 0
68 9 90000 10000 0 0 256 36 10 4096 722 0 0 35 65536 0 0 65536 0 0
69 10 100000 10000 0 0 256 36 11 4096 978 0 0 41 42 65536 0 0 65536 0 0
70 11 110000 10000 0 0 256 36 11 4096 1234 0 0 48 65536 0 0 65536 0 0
71 12 120000 10000 0 0 256 36 12 4096 1490 0 0 54 55 65536 0 0 65536 0 0
72 13 130000 10000 0 0 256 37 12 4096 1746 0 0 61 65536 0 0 65536 0 0
73 14 140000 10000 0 0 230 39 12 4096 1949 0 0 67 65536 0 0 65536 0 0
74 15 150000 10000 0 0 256 39 13 4096 2204 0 0 73 65536 0 0 65536 0 0
84 25 250000 10000 0 0 256 43 20 2048 2048 0 0 140 65536 0 1 65536 0 0
85 26 260000 10000 0 0 256 45 21 2048 2048 0 0 147 65536 0 1 65536 0 0
86 27 270000 10000 0 0 256 45 22 1024 1024 0 0 153 65536 0 1 65536 0 0
87 28 280000 10000 0 0 256 45 23 1024 1024 0 0 160 159 65536 0 1 65536 0 0
88 29 290000 10000 0 0 256 45 24 512 512 0 0 166 65536 0 1 65536 0 0
89 30 300000 10000 0 0 256 45 24 512 512 0 0 173 172 65536 0 1 65536 0 0
90 31 310000 10000 0 0 256 45 25 256 256 0 0 180 179 65536 0 1 65536 0 0
91 32 320000 10000 0 0 255 45 26 256 256 0 0 186 185 65536 0 1 65536 0 0
92 33 330000 10000 0 0 256 45 27 256 256 0 0 193 192 65536 0 1 65536 0 0
93 34 340000 10000 0 0 256 45 27 256 256 0 0 199 198 65536 0 1 65536 0 0
94 35 350000 10000 0 0 256 45 28 256 256 0 0 207 205 65536 0 1 65536 0 0
95 36 360000 10000 0 0 256 45 29 256 256 0 0 221 211 65536 0 1 65536 0 0
experiments/bare_metal/runs/doe-aarch64-20260808-093228.csv
+95
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@@ -0,0 +1,95 @@
tick_number,elapsed_ns,tick_interval_ns,cache_hits_delta,bucket_hits_delta,word_executions_delta,hot_word_count,avg_word_heat_q48,window_width,actual_window_size,predicted_label_hits,jitter_bits,apic_ticks,time_trust_q48,variance_q48,vm_call_depth_max,hera_heat_q48,hermes_heat_q48,artemis_heat_q48
1,10000,10000,0,0,183,4,45,731,731,0,0,0,65536,0,0,65536,0,0
2,20000,10000,0,0,173,5,44,582,582,0,0,0,65536,0,0,65536,0,0
3,30000,10000,0,0,184,6,60,582,582,0,0,0,65536,0,0,65536,0,0
4,40000,10000,0,0,174,8,71,4096,0,0,0,0,65536,0,0,65536,0,0
5,50000,10000,0,0,150,9,78,582,582,0,0,0,65536,0,0,65536,0,0
6,60000,10000,0,0,159,11,73,4096,0,0,0,0,65536,0,0,65536,0,0
7,70000,10000,0,0,188,15,71,685,685,0,0,0,65536,0,0,65536,0,0
8,80000,10000,0,0,214,16,83,685,685,0,0,0,65536,0,0,65536,0,0
9,90000,10000,0,0,216,19,82,4096,0,0,0,0,65536,0,0,65536,0,0
10,100000,10000,0,0,222,21,84,567,567,0,0,0,65536,0,0,65536,0,0
11,110000,10000,0,0,207,23,86,731,731,0,0,0,65536,0,0,65536,0,0
12,120000,10000,0,0,189,26,83,4096,0,0,0,0,65536,0,0,65536,0,0
13,130000,10000,0,0,221,28,80,731,731,0,0,0,65536,0,0,65536,0,0
14,140000,10000,0,0,204,29,83,685,685,0,0,0,65536,0,0,65536,0,0
15,150000,10000,0,0,203,30,82,731,731,0,0,0,65536,0,0,65536,0,0
16,160000,10000,0,0,201,32,83,567,567,0,0,0,65536,0,0,65536,0,0
17,170000,10000,0,0,190,34,86,731,731,0,0,0,65536,0,0,65536,0,0
18,180000,10000,0,0,170,35,73,582,582,0,0,0,65536,0,0,65536,0,0
19,190000,10000,0,0,154,28,44,731,731,0,0,0,65536,0,0,65536,0,0
20,200000,10000,0,0,154,28,41,567,567,0,0,0,65536,0,0,65536,0,0
21,210000,10000,0,0,153,32,39,4096,0,0,0,0,65536,0,0,65536,0,0
22,220000,10000,0,0,167,35,42,582,582,0,0,0,65536,0,0,65536,0,0
23,230000,10000,0,0,176,37,41,685,685,0,0,0,65536,0,0,65536,0,0
24,240000,10000,0,0,175,37,39,731,731,0,0,0,65536,0,0,65536,0,0
25,250000,10000,0,0,196,38,37,731,731,0,0,0,65536,0,0,65536,0,0
26,260000,10000,0,0,192,41,37,4096,0,0,0,0,65536,0,0,65536,0,0
27,270000,10000,0,0,158,40,38,685,685,0,0,0,65536,0,0,65536,0,0
28,280000,10000,0,0,158,40,35,4096,0,0,0,0,65536,0,0,65536,0,0
29,290000,10000,0,0,164,41,37,4096,0,0,0,0,65536,0,0,65536,0,0
30,300000,10000,0,0,154,43,39,685,685,0,0,0,65536,0,0,65536,0,0
31,310000,10000,0,0,172,46,35,582,582,0,0,0,65536,0,0,65536,0,0
32,320000,10000,0,0,180,49,34,567,567,0,0,0,65536,0,0,65536,0,0
33,330000,10000,0,0,145,51,35,567,567,0,0,0,65536,0,0,65536,0,0
34,340000,10000,0,0,203,53,37,582,582,0,0,0,65536,0,0,65536,0,0
35,350000,10000,0,0,154,55,39,731,731,0,0,0,65536,0,0,65536,0,0
36,360000,10000,0,0,144,57,37,4096,0,0,0,0,65536,0,0,65536,0,0
37,370000,10000,0,0,144,57,35,4096,0,0,0,0,65536,0,0,65536,0,0
38,380000,10000,0,0,132,57,34,4096,0,0,0,0,65536,0,0,65536,0,0
39,390000,10000,0,0,180,57,32,4096,0,0,0,0,65536,0,0,65536,0,0
40,400000,10000,0,0,220,63,29,4096,0,0,0,0,65536,0,0,65536,0,0
41,410000,10000,0,0,215,64,28,4096,24,0,0,0,65536,0,0,65536,0,0
42,420000,10000,0,0,208,68,29,4096,24,0,0,0,65536,0,0,65536,0,0
43,430000,10000,0,0,177,72,27,4096,24,0,0,0,65536,0,0,65536,0,0
44,440000,10000,0,0,199,77,28,4096,24,0,0,0,65536,0,0,65536,0,0
45,450000,10000,0,0,223,82,26,4096,30,0,0,0,65536,0,0,65536,0,0
46,460000,10000,0,0,202,85,24,4096,67,0,0,0,65536,0,0,65536,0,0
47,470000,10000,0,0,218,91,25,4096,198,0,0,0,65536,0,0,65536,0,0
48,480000,10000,0,0,221,92,26,4096,350,0,0,0,65536,0,0,65536,0,0
49,490000,10000,0,0,225,97,26,4096,528,0,0,0,65536,0,0,65536,0,0
50,500000,10000,0,0,214,100,27,4096,694,0,0,0,65536,0,0,65536,0,0
51,510000,10000,0,0,227,102,28,4096,883,0,0,0,65536,0,0,65536,0,0
52,520000,10000,0,0,208,102,29,4096,1043,0,0,0,65536,0,0,65536,0,0
53,530000,10000,0,0,207,102,30,4096,1202,0,0,0,65536,0,0,65536,0,0
54,540000,10000,0,0,200,102,31,4096,1319,0,0,0,65536,0,0,65536,0,0
55,550000,10000,0,0,205,103,32,4096,1464,0,0,0,65536,0,0,65536,0,0
56,560000,10000,0,0,211,103,32,4096,1620,0,0,0,65536,0,0,65536,0,0
57,570000,10000,0,0,193,110,33,4096,1712,0,0,0,65536,0,0,65536,0,0
58,580000,10000,0,0,190,5,67,4096,1775,0,0,0,65536,0,0,65536,0,0
1,10000,18446744073708981616,0,0,117,4,4,4096,0,0,4895412794951728869,10,65536,0,0,65536,0,0
2,20000,10000,0,0,78,10,7,4096,0,0,0,11,65536,0,0,65536,0,0
3,30000,10000,0,0,101,13,7,4096,0,0,0,12,65536,0,0,65536,0,0
4,40000,10000,0,0,63,19,8,4096,0,0,0,13,65536,0,0,65536,0,0
5,50000,10000,0,0,92,25,8,4096,2,0,0,15,65536,0,0,65536,0,0
6,60000,10000,0,0,64,27,8,4096,2,0,0,16,65536,0,0,65536,0,0
7,70000,10000,0,0,228,32,8,4096,210,0,0,22,65536,0,0,65536,0,0
8,80000,10000,0,0,256,34,9,4096,466,0,0,29,65536,0,0,65536,0,0
9,90000,10000,0,0,256,36,10,4096,722,0,0,35,65536,0,0,65536,0,0
10,100000,10000,0,0,256,36,11,4096,978,0,0,42,65536,0,0,65536,0,0
11,110000,10000,0,0,256,36,11,4096,1234,0,0,48,65536,0,0,65536,0,0
12,120000,10000,0,0,256,36,12,4096,1490,0,0,55,65536,0,0,65536,0,0
13,130000,10000,0,0,256,37,12,4096,1746,0,0,61,65536,0,0,65536,0,0
14,140000,10000,0,0,230,39,12,4096,1949,0,0,67,65536,0,0,65536,0,0
15,150000,10000,0,0,256,39,13,4096,2204,0,0,73,65536,0,0,65536,0,0
16,160000,10000,0,0,256,39,14,4096,2459,0,0,80,65536,0,0,65536,0,0
17,170000,10000,0,0,256,39,15,4096,2713,0,0,86,65536,0,0,65536,0,0
18,180000,10000,0,0,256,39,15,4096,2969,0,0,93,65536,0,0,65536,0,0
19,190000,10000,0,0,256,39,16,4096,3224,0,0,99,65536,0,1,65536,0,0
20,200000,10000,0,0,256,41,17,4096,3480,0,0,106,65536,0,1,65536,0,0
21,210000,10000,0,0,256,41,17,4096,3736,0,0,114,65536,0,1,65536,0,0
22,220000,10000,0,0,256,41,18,4096,3992,0,0,121,65536,0,1,65536,0,0
23,230000,10000,0,0,256,41,19,4096,4096,0,0,127,65536,0,1,65536,0,0
24,240000,10000,0,0,256,41,20,4096,4096,0,0,134,65536,0,1,65536,0,0
25,250000,10000,0,0,256,43,20,2048,2048,0,0,140,65536,0,1,65536,0,0
26,260000,10000,0,0,256,45,21,2048,2048,0,0,147,65536,0,1,65536,0,0
27,270000,10000,0,0,256,45,22,1024,1024,0,0,153,65536,0,1,65536,0,0
28,280000,10000,0,0,256,45,23,1024,1024,0,0,159,65536,0,1,65536,0,0
29,290000,10000,0,0,256,45,24,512,512,0,0,166,65536,0,1,65536,0,0
30,300000,10000,0,0,256,45,24,512,512,0,0,172,65536,0,1,65536,0,0
31,310000,10000,0,0,256,45,25,256,256,0,0,179,65536,0,1,65536,0,0
32,320000,10000,0,0,255,45,26,256,256,0,0,185,65536,0,1,65536,0,0
33,330000,10000,0,0,256,45,27,256,256,0,0,192,65536,0,1,65536,0,0
34,340000,10000,0,0,256,45,27,256,256,0,0,198,65536,0,1,65536,0,0
35,350000,10000,0,0,256,45,28,256,256,0,0,205,65536,0,1,65536,0,0
36,360000,10000,0,0,256,45,29,256,256,0,0,211,65536,0,1,65536,0,0
1 tick_number elapsed_ns tick_interval_ns cache_hits_delta bucket_hits_delta word_executions_delta hot_word_count avg_word_heat_q48 window_width actual_window_size predicted_label_hits jitter_bits apic_ticks time_trust_q48 variance_q48 vm_call_depth_max hera_heat_q48 hermes_heat_q48 artemis_heat_q48
2 1 10000 10000 0 0 183 4 45 731 731 0 0 0 65536 0 0 65536 0 0
3 2 20000 10000 0 0 173 5 44 582 582 0 0 0 65536 0 0 65536 0 0
4 3 30000 10000 0 0 184 6 60 582 582 0 0 0 65536 0 0 65536 0 0
5 4 40000 10000 0 0 174 8 71 4096 0 0 0 0 65536 0 0 65536 0 0
6 5 50000 10000 0 0 150 9 78 582 582 0 0 0 65536 0 0 65536 0 0
7 6 60000 10000 0 0 159 11 73 4096 0 0 0 0 65536 0 0 65536 0 0
8 7 70000 10000 0 0 188 15 71 685 685 0 0 0 65536 0 0 65536 0 0
9 8 80000 10000 0 0 214 16 83 685 685 0 0 0 65536 0 0 65536 0 0
10 9 90000 10000 0 0 216 19 82 4096 0 0 0 0 65536 0 0 65536 0 0
11 10 100000 10000 0 0 222 21 84 567 567 0 0 0 65536 0 0 65536 0 0
12 11 110000 10000 0 0 207 23 86 731 731 0 0 0 65536 0 0 65536 0 0
13 12 120000 10000 0 0 189 26 83 4096 0 0 0 0 65536 0 0 65536 0 0
14 13 130000 10000 0 0 221 28 80 731 731 0 0 0 65536 0 0 65536 0 0
15 14 140000 10000 0 0 204 29 83 685 685 0 0 0 65536 0 0 65536 0 0
16 15 150000 10000 0 0 203 30 82 731 731 0 0 0 65536 0 0 65536 0 0
17 16 160000 10000 0 0 201 32 83 567 567 0 0 0 65536 0 0 65536 0 0
18 17 170000 10000 0 0 190 34 86 731 731 0 0 0 65536 0 0 65536 0 0
19 18 180000 10000 0 0 170 35 73 582 582 0 0 0 65536 0 0 65536 0 0
20 19 190000 10000 0 0 154 28 44 731 731 0 0 0 65536 0 0 65536 0 0
21 20 200000 10000 0 0 154 28 41 567 567 0 0 0 65536 0 0 65536 0 0
22 21 210000 10000 0 0 153 32 39 4096 0 0 0 0 65536 0 0 65536 0 0
23 22 220000 10000 0 0 167 35 42 582 582 0 0 0 65536 0 0 65536 0 0
24 23 230000 10000 0 0 176 37 41 685 685 0 0 0 65536 0 0 65536 0 0
25 24 240000 10000 0 0 175 37 39 731 731 0 0 0 65536 0 0 65536 0 0
26 25 250000 10000 0 0 196 38 37 731 731 0 0 0 65536 0 0 65536 0 0
27 26 260000 10000 0 0 192 41 37 4096 0 0 0 0 65536 0 0 65536 0 0
28 27 270000 10000 0 0 158 40 38 685 685 0 0 0 65536 0 0 65536 0 0
29 28 280000 10000 0 0 158 40 35 4096 0 0 0 0 65536 0 0 65536 0 0
30 29 290000 10000 0 0 164 41 37 4096 0 0 0 0 65536 0 0 65536 0 0
31 30 300000 10000 0 0 154 43 39 685 685 0 0 0 65536 0 0 65536 0 0
32 31 310000 10000 0 0 172 46 35 582 582 0 0 0 65536 0 0 65536 0 0
33 32 320000 10000 0 0 180 49 34 567 567 0 0 0 65536 0 0 65536 0 0
34 33 330000 10000 0 0 145 51 35 567 567 0 0 0 65536 0 0 65536 0 0
35 34 340000 10000 0 0 203 53 37 582 582 0 0 0 65536 0 0 65536 0 0
36 35 350000 10000 0 0 154 55 39 731 731 0 0 0 65536 0 0 65536 0 0
37 36 360000 10000 0 0 144 57 37 4096 0 0 0 0 65536 0 0 65536 0 0
38 37 370000 10000 0 0 144 57 35 4096 0 0 0 0 65536 0 0 65536 0 0
39 38 380000 10000 0 0 132 57 34 4096 0 0 0 0 65536 0 0 65536 0 0
40 39 390000 10000 0 0 180 57 32 4096 0 0 0 0 65536 0 0 65536 0 0
41 40 400000 10000 0 0 220 63 29 4096 0 0 0 0 65536 0 0 65536 0 0
42 41 410000 10000 0 0 215 64 28 4096 24 0 0 0 65536 0 0 65536 0 0
43 42 420000 10000 0 0 208 68 29 4096 24 0 0 0 65536 0 0 65536 0 0
44 43 430000 10000 0 0 177 72 27 4096 24 0 0 0 65536 0 0 65536 0 0
45 44 440000 10000 0 0 199 77 28 4096 24 0 0 0 65536 0 0 65536 0 0
46 45 450000 10000 0 0 223 82 26 4096 30 0 0 0 65536 0 0 65536 0 0
47 46 460000 10000 0 0 202 85 24 4096 67 0 0 0 65536 0 0 65536 0 0
48 47 470000 10000 0 0 218 91 25 4096 198 0 0 0 65536 0 0 65536 0 0
49 48 480000 10000 0 0 221 92 26 4096 350 0 0 0 65536 0 0 65536 0 0
50 49 490000 10000 0 0 225 97 26 4096 528 0 0 0 65536 0 0 65536 0 0
51 50 500000 10000 0 0 214 100 27 4096 694 0 0 0 65536 0 0 65536 0 0
52 51 510000 10000 0 0 227 102 28 4096 883 0 0 0 65536 0 0 65536 0 0
53 52 520000 10000 0 0 208 102 29 4096 1043 0 0 0 65536 0 0 65536 0 0
54 53 530000 10000 0 0 207 102 30 4096 1202 0 0 0 65536 0 0 65536 0 0
55 54 540000 10000 0 0 200 102 31 4096 1319 0 0 0 65536 0 0 65536 0 0
56 55 550000 10000 0 0 205 103 32 4096 1464 0 0 0 65536 0 0 65536 0 0
57 56 560000 10000 0 0 211 103 32 4096 1620 0 0 0 65536 0 0 65536 0 0
58 57 570000 10000 0 0 193 110 33 4096 1712 0 0 0 65536 0 0 65536 0 0
59 58 580000 10000 0 0 190 5 67 4096 1775 0 0 0 65536 0 0 65536 0 0
60 1 10000 18446744073708981616 0 0 117 4 4 4096 0 0 4895412794951728869 10 65536 0 0 65536 0 0
61 2 20000 10000 0 0 78 10 7 4096 0 0 0 11 65536 0 0 65536 0 0
62 3 30000 10000 0 0 101 13 7 4096 0 0 0 12 65536 0 0 65536 0 0
63 4 40000 10000 0 0 63 19 8 4096 0 0 0 13 65536 0 0 65536 0 0
64 5 50000 10000 0 0 92 25 8 4096 2 0 0 15 65536 0 0 65536 0 0
65 6 60000 10000 0 0 64 27 8 4096 2 0 0 16 65536 0 0 65536 0 0
66 7 70000 10000 0 0 228 32 8 4096 210 0 0 22 65536 0 0 65536 0 0
67 8 80000 10000 0 0 256 34 9 4096 466 0 0 29 65536 0 0 65536 0 0
68 9 90000 10000 0 0 256 36 10 4096 722 0 0 35 65536 0 0 65536 0 0
69 10 100000 10000 0 0 256 36 11 4096 978 0 0 42 65536 0 0 65536 0 0
70 11 110000 10000 0 0 256 36 11 4096 1234 0 0 48 65536 0 0 65536 0 0
71 12 120000 10000 0 0 256 36 12 4096 1490 0 0 55 65536 0 0 65536 0 0
72 13 130000 10000 0 0 256 37 12 4096 1746 0 0 61 65536 0 0 65536 0 0
73 14 140000 10000 0 0 230 39 12 4096 1949 0 0 67 65536 0 0 65536 0 0
74 15 150000 10000 0 0 256 39 13 4096 2204 0 0 73 65536 0 0 65536 0 0
75 16 160000 10000 0 0 256 39 14 4096 2459 0 0 80 65536 0 0 65536 0 0
76 17 170000 10000 0 0 256 39 15 4096 2713 0 0 86 65536 0 0 65536 0 0
77 18 180000 10000 0 0 256 39 15 4096 2969 0 0 93 65536 0 0 65536 0 0
78 19 190000 10000 0 0 256 39 16 4096 3224 0 0 99 65536 0 1 65536 0 0
79 20 200000 10000 0 0 256 41 17 4096 3480 0 0 106 65536 0 1 65536 0 0
80 21 210000 10000 0 0 256 41 17 4096 3736 0 0 114 65536 0 1 65536 0 0
81 22 220000 10000 0 0 256 41 18 4096 3992 0 0 121 65536 0 1 65536 0 0
82 23 230000 10000 0 0 256 41 19 4096 4096 0 0 127 65536 0 1 65536 0 0
83 24 240000 10000 0 0 256 41 20 4096 4096 0 0 134 65536 0 1 65536 0 0
84 25 250000 10000 0 0 256 43 20 2048 2048 0 0 140 65536 0 1 65536 0 0
85 26 260000 10000 0 0 256 45 21 2048 2048 0 0 147 65536 0 1 65536 0 0
86 27 270000 10000 0 0 256 45 22 1024 1024 0 0 153 65536 0 1 65536 0 0
87 28 280000 10000 0 0 256 45 23 1024 1024 0 0 159 65536 0 1 65536 0 0
88 29 290000 10000 0 0 256 45 24 512 512 0 0 166 65536 0 1 65536 0 0
89 30 300000 10000 0 0 256 45 24 512 512 0 0 172 65536 0 1 65536 0 0
90 31 310000 10000 0 0 256 45 25 256 256 0 0 179 65536 0 1 65536 0 0
91 32 320000 10000 0 0 255 45 26 256 256 0 0 185 65536 0 1 65536 0 0
92 33 330000 10000 0 0 256 45 27 256 256 0 0 192 65536 0 1 65536 0 0
93 34 340000 10000 0 0 256 45 27 256 256 0 0 198 65536 0 1 65536 0 0
94 35 350000 10000 0 0 256 45 28 256 256 0 0 205 65536 0 1 65536 0 0
95 36 360000 10000 0 0 256 45 29 256 256 0 0 211 65536 0 1 65536 0 0
logs/20260808-093228/aarch64/qemu-aarch64-20260808-093228.log
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