Robert Allan JamesandClaude Sonnet 5
ca52ce8243
New include/starkernel/rpi5_dtb.h / src/starkernel/arch/aarch64/rpi5_dtb.c:
rpi5_uart_base()/rpi5_mailbox_base(), each finding their peripheral by
compatible string ("arm,pl011" / "brcm,bcm2835-mbox") via fdt_find_node_by_
compatible() then reading its "reg" via fdt_find_prop_in_node().
Found and fixed a real translation gap before it could have silently
produced a wrong address: confirmed directly against bcm2712.dtsi
(raspberrypi/linux) that both peripherals live under one "soc"
simple-bus node whose ranges property adds a fixed 0x10_0000_0000
offset to every child reg value. fdt.c's reader deliberately doesn't
apply ranges translation generally (not a general devicetree
library); this file applies that one, fixed, SoC-wide offset
explicitly, documented with the exact devicetree excerpt that
confirmed it.
Compile-only verification -- no caller wired in yet, these two
functions are what the still-open entry-stub and mailbox-framebuffer-
driver punch-list items will call. Verified 3-arch boot to ok>
(amd64/aarch64/riscv64, each in the foreground; rpi5_dtb.o confirmed
built on aarch64, the only arch that compiles this file).
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_019YcT3H2PQeyujrzjqS3Var
94 lines
3.2 KiB
C
94 lines
3.2 KiB
C
/*
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StarForth — Steady-State Virtual Machine Runtime
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Copyright (c) 2023–2025 Robert A. James. All rights reserved.
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Licensed under the StarForth License, Version 1.0.
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*/
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/**
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* rpi5_dtb.c - Raspberry Pi 5 (BCM2712) devicetree-based peripheral
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* discovery (FABRIC-3.md §IV.3, 2026-09-04).
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*
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* Confirmed directly against `bcm2712.dtsi` (raspberrypi/linux,
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* rpi-6.12.y) before writing this, not assumed:
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*
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* soc: soc@107c000000 {
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* compatible = "simple-bus";
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* ranges = <0x0 0x10 0x0 0x80000000>;
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* #address-cells = <1>;
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* #size-cells = <1>;
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* ...
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* uart10: serial@7d001000 {
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* compatible = "arm,pl011", "arm,primecell";
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* reg = <0x7d001000 0x200>;
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* };
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* mailbox: mailbox@7c013880 {
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* compatible = "brcm,bcm2835-mbox";
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* reg = <0x7c013880 0x40>;
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* };
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* };
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*
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* Every peripheral this file cares about lives under this one "soc"
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* node, which applies exactly one translation to every child `reg`
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* value: child address 0 maps to parent (CPU-physical) address
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* 0x10_0000_0000 (`ranges`'s own `<0x0 0x10 0x0 ...>` — child cell 0,
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* parent cells `0x10 0x0`, i.e. `0x10 << 32`). The child side's own
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* `#address-cells = <1>` confirms each `reg` value's first cell is the
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* whole child address (32-bit, no cell-splitting needed) before adding
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* the offset. `fdt.c`'s reader deliberately does not parse `ranges`
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* generally (it is "not a general devicetree library," per its own
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* header comment) — this one, fixed, SoC-wide offset is applied here
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* by name instead, since it is a single known hardware fact, not a
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* general mechanism this codebase needs elsewhere yet.
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*/
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#include "starkernel/rpi5_dtb.h"
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#include "starkernel/fdt.h"
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/* soc@107c000000's own `ranges` offset -- see this file's own doc
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* comment above for where it was confirmed. */
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#define BCM2712_SOC_RANGES_OFFSET 0x1000000000ULL
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/**
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* @brief Read a devicetree `reg` property's first cell as big-endian.
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*
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* `fdt.c` keeps its own `be32()` helper file-local (freestanding, no
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* shared byte-swap utility to reuse) -- duplicated here rather than
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* exposing it, same "a few lines is simpler than a new shared
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* dependency" precedent `tools/pkcs8_ed25519.c` already set in this
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* codebase.
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*/
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static uint32_t reg_first_cell_be32(const unsigned char* b)
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{
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return ((uint32_t) b[0] << 24) | ((uint32_t) b[1] << 16) |
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((uint32_t) b[2] << 8) | (uint32_t) b[3];
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}
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/**
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* @brief Find @p compatible's node, read its `reg` base address, and
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* apply the one fixed BCM2712 `soc`-node translation offset.
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*/
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static uint64_t rpi5_peripheral_base(const void* dtb, const char* compatible)
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{
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const void* node;
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const void* val;
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uint32_t len;
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node = fdt_find_node_by_compatible(dtb, compatible);
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if (!node) return 0;
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val = fdt_find_prop_in_node(dtb, node, "reg", &len);
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if (!val || len < 4) return 0;
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return BCM2712_SOC_RANGES_OFFSET + reg_first_cell_be32((const unsigned char*) val);
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}
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uint64_t rpi5_uart_base(const void* dtb)
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{
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return rpi5_peripheral_base(dtb, "arm,pl011");
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}
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uint64_t rpi5_mailbox_base(const void* dtb)
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{
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return rpi5_peripheral_base(dtb, "brcm,bcm2835-mbox");
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}
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