Robert Allan JamesandClaude Sonnet 5
8251aebcf8
Punch list §25 item 4.3.5c complete. Amended from a nonexistent MMIO transport to PCI (matching the board's actual virtio-blk-pci precedent). New virtio-input driver: eventq with pre-posted buffers, PLIC source computed at runtime from PCI slot/pin (derived live from this host's QEMU riscv64 DTB), mandatory ISR-status read, PCI interrupt-disable-bit check. New VKBD-EVENT/VKBD-DEBUG FORTH words. Verified with a real QEMU sendkey keypress: exact KEY_A/press match, two real interrupts serviced, zero exceptions. Three-arch acceptance boot clean. Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
105 lines
3.6 KiB
C
105 lines
3.6 KiB
C
/*
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* pci.h — Generic PCI/PCIe subsystem for StarKernel
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*
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* Config space access:
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* amd64 — Type 1 port I/O (CF8/CFC); no memory mapping required.
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* others — ECAM via ACPI MCFG; UEFI identity-maps the ECAM window.
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*
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* BAR MMIO:
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* Call pci_map_bar() before the first MMIO access. On amd64 this
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* adds a VMM page-table mapping (cache-disabled); on other arches
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* the UEFI tables already cover the region and the call is a no-op.
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*/
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#ifndef STARKERNEL_PCI_H
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#define STARKERNEL_PCI_H
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#include <stdint.h>
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/* PCI standard config-space offsets */
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#define PCI_CFG_VENDOR_ID 0x00
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#define PCI_CFG_DEVICE_ID 0x02
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#define PCI_CFG_COMMAND 0x04
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#define PCI_CFG_STATUS 0x06
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#define PCI_CFG_CLASS_REV 0x08
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#define PCI_CFG_HEADER_TYPE 0x0E
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#define PCI_CFG_BAR0 0x10
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#define PCI_CFG_BAR1 0x14
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#define PCI_CFG_BAR2 0x18
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#define PCI_CFG_BAR3 0x1C
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#define PCI_CFG_BAR4 0x20
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#define PCI_CFG_BAR5 0x24
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#define PCI_CFG_CAP_PTR 0x34
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#define PCI_CFG_INT_LINE 0x3C
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#define PCI_CFG_INT_PIN 0x3D /* 0=none, 1=INTA .. 4=INTD (item 4.3.5c/4.3.5d) */
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/* PCI command register bits */
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#define PCI_CMD_IO_SPACE (1u << 0)
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#define PCI_CMD_MEM_SPACE (1u << 1)
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#define PCI_CMD_BUS_MASTER (1u << 2)
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#define PCI_CMD_INTX_DISABLE (1u << 10) /* item 4.3.5c/4.3.5e: pci_enable() never
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* clears this -- if firmware left it set,
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* INTx never asserts. Check explicitly. */
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/* BAR type flags */
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#define PCI_BAR_TYPE_MASK 0x1u
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#define PCI_BAR_IO 0x1u
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#define PCI_BAR_MEM_64 0x4u /* bits [2:1] == 10 in memory BAR */
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/* Identified PCI device */
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typedef struct {
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uint8_t bus;
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uint8_t device;
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uint8_t function;
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uint16_t vendor_id;
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uint16_t device_id;
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} PciDevice;
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/*
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* pci_init — parse ACPI RSDP → XSDT → MCFG to find ECAM base.
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* On amd64, also maps the ECAM window via the VMM.
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* May be called with rsdp==NULL; port-I/O fallback still works
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* on amd64. On aarch64/riscv64 ECAM is required.
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* Returns 0 on success, -1 if no ECAM found (amd64 still functional via
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* port I/O).
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*/
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int pci_init(void *rsdp);
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/*
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* pci_find_first — linear scan of bus 0 for the first device matching
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* (vendor_id, device_id). Fill *out on match.
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* Returns 0 on found, -1 if not found.
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*/
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int pci_find_first(uint16_t vendor_id, uint16_t device_id, PciDevice *out);
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/* Config space accessors */
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uint32_t pci_read32 (const PciDevice *d, uint16_t offset);
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uint16_t pci_read16 (const PciDevice *d, uint16_t offset);
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uint8_t pci_read8 (const PciDevice *d, uint16_t offset);
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void pci_write32(const PciDevice *d, uint16_t offset, uint32_t val);
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void pci_write16(const PciDevice *d, uint16_t offset, uint16_t val);
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void pci_write8 (const PciDevice *d, uint16_t offset, uint8_t val);
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/*
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* pci_enable — set I/O space + memory space + bus-master bits in the
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* PCI command register.
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*/
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void pci_enable(const PciDevice *d);
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/*
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* pci_bar — return the base address (physical) of BAR bar_idx.
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* Handles 32-bit and 64-bit memory BARs; returns 0 for I/O BARs.
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* Does NOT map the region — call pci_map_bar() separately.
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*/
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uint64_t pci_bar(const PciDevice *d, int bar_idx);
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/*
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* pci_map_bar — make the BAR MMIO region accessible.
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* amd64: calls vmm_map_range(phys, phys, size, WR|CD).
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* others: no-op (UEFI identity map covers it).
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* Returns 0 on success, -1 on failure.
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*/
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int pci_map_bar(uint64_t phys_addr, uint64_t size);
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#endif /* STARKERNEL_PCI_H */
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